Issued Patents 2023
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11853556 | Combining sets of memory blocks in a memory device | Steven Michael Kientz, Larry J. Koudele, Shane Nowell, Bruce A. Liikanen | 2023-12-26 |
| 11842772 | Voltage bin boundary calibration at memory device power up | Bruce A. Liikanen, Steve Kientz | 2023-12-12 |
| 11842061 | Open block family duration limited by temperature variation | Larry J. Koudele, Bruce A. Liikanen, Steven Michael Kientz | 2023-12-12 |
| 11837291 | Voltage offset bin selection by die group for memory devices | Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Larry J. Koudele, Shane Nowell | 2023-12-05 |
| 11817152 | Generating embedded data in memory cells in a memory sub-system | Bruce A. Liikanen, Larry J. Koudele | 2023-11-14 |
| 11810631 | Data integrity checks based on voltage distribution metrics | Vamsi Pavan Rayaprolu, Christopher M. Smitchger | 2023-11-07 |
| 11789640 | Estimation of read level thresholds using a data structure | Larry J. Koudele, Bruce A. Liikanen | 2023-10-17 |
| 11791004 | Threshold voltage offset bin selection based on die family in memory devices | Bruce A. Liikanen, Steve Kientz, Anita Ekren, Gerald L. Cadloni | 2023-10-17 |
| 11768619 | Voltage based combining of block families for memory devices | Kishore Kumar Muchherla, Shane Nowell | 2023-09-26 |
| 11755478 | Block family combination and voltage bin selection | Larry J. Koudele, Mustafa N. Kaynak, Shane Nowell | 2023-09-12 |
| 11742027 | Dynamic program erase targeting with bit error rate | Bruce A. Liikanen, Larry J. Koudele | 2023-08-29 |
| 11733928 | Read sample offset bit determination in a memory sub-system | Bruce A. Liikanen | 2023-08-22 |
| 11735254 | Error avoidance based on voltage distribution parameters of blocks | Shane Nowell, Steven Michael Kientz, Mustafa N. Kaynak, Kishore Kumar Muchherla, Larry J. Koudele +1 more | 2023-08-22 |
| 11733929 | Memory system with dynamic calibration using a variable adjustment mechanism | Larry J. Koudele, Steve Kientz | 2023-08-22 |
| 11733896 | Reliability scan assisted voltage bin selection | Vamsi Pavan Rayaprolu, Shane Nowell | 2023-08-22 |
| 11727994 | Performing threshold voltage offset bin selection by package for memory devices | Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Larry J. Koudele | 2023-08-15 |
| 11726689 | Time-based combining for block families of a memory device | Shane Nowell, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla | 2023-08-15 |
| 11721399 | Memory system with dynamic calibration using a trim management mechanism | Larry J. Koudele, Steve Kientz | 2023-08-08 |
| 11721409 | Smart sampling for block family scan | Vamsi Pavan Rayaprolu, Shane Nowell, Steven Michael Kientz | 2023-08-08 |
| 11714580 | Dynamic background scan optimization in a memory sub-system | Gerald L. Cadloni, Francis Chew, Bruce A. Liikanen, Larry J. Koudele | 2023-08-01 |
| 11714710 | Providing data of a memory system based on an adjustable error rate | Mustafa N. Kaynak, Larry J. Koudele, Patrick R. Khayat, Sampath K. Ratnam | 2023-08-01 |
| 11709775 | Write data for bin resynchronization after power loss | Bruce A. Liikanen, Steven Michael Kientz | 2023-07-25 |
| 11704217 | Charge loss scan operation management in memory devices | Steven Michael Kientz, Shane Nowell, Mustafa N. Kaynak, Kishore Kumar Muchherla, Larry J. Koudele | 2023-07-18 |
| 11705208 | Read level calibration in memory devices using embedded servo cells | Larry J. Koudele, Bruce A. Liikanen | 2023-07-18 |
| 11705193 | Error avoidance based on voltage distribution parameters | Shane Nowell, Steven Michael Kientz, Mustafa N. Kaynak, Kishore Kumar Muchherla, Larry J. Koudele +1 more | 2023-07-18 |