Issued Patents 2023
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11853556 | Combining sets of memory blocks in a memory device | Steven Michael Kientz, Larry J. Koudele, Shane Nowell, Michael Sheperek | 2023-12-26 |
| 11842772 | Voltage bin boundary calibration at memory device power up | Michael Sheperek, Steve Kientz | 2023-12-12 |
| 11842061 | Open block family duration limited by temperature variation | Michael Sheperek, Larry J. Koudele, Steven Michael Kientz | 2023-12-12 |
| 11836345 | Memory element profiling and operational adjustments | Francis Chew | 2023-12-05 |
| 11817152 | Generating embedded data in memory cells in a memory sub-system | Michael Sheperek, Larry J. Koudele | 2023-11-14 |
| 11789640 | Estimation of read level thresholds using a data structure | Michael Sheperek, Larry J. Koudele | 2023-10-17 |
| 11791004 | Threshold voltage offset bin selection based on die family in memory devices | Michael Sheperek, Steve Kientz, Anita Ekren, Gerald L. Cadloni | 2023-10-17 |
| 11748008 | Changing of memory components to be used for a stripe based on an endurance condition | — | 2023-09-05 |
| 11742027 | Dynamic program erase targeting with bit error rate | Michael Sheperek, Larry J. Koudele | 2023-08-29 |
| 11733928 | Read sample offset bit determination in a memory sub-system | Michael Sheperek | 2023-08-22 |
| 11735254 | Error avoidance based on voltage distribution parameters of blocks | Shane Nowell, Steven Michael Kientz, Michael Sheperek, Mustafa N. Kaynak, Kishore Kumar Muchherla +1 more | 2023-08-22 |
| 11727994 | Performing threshold voltage offset bin selection by package for memory devices | Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Larry J. Koudele | 2023-08-15 |
| 11714709 | Enhanced block management for a memory subsystem | Gerald L. Cadloni | 2023-08-01 |
| 11715530 | Offset memory component automatic calibration (autocal) error recovery for a memory sub-system | Gerald L. Cadloni, Gary F. Besinga, Michael G. Miller, Renato C. Padilla | 2023-08-01 |
| 11714580 | Dynamic background scan optimization in a memory sub-system | Gerald L. Cadloni, Michael Sheperek, Francis Chew, Larry J. Koudele | 2023-08-01 |
| 11709775 | Write data for bin resynchronization after power loss | Michael Sheperek, Steven Michael Kientz | 2023-07-25 |
| 11705215 | Memory sub-system with background scan and histogram statistics | Gerald L. Cadloni | 2023-07-18 |
| 11705208 | Read level calibration in memory devices using embedded servo cells | Larry J. Koudele, Michael Sheperek | 2023-07-18 |
| 11705193 | Error avoidance based on voltage distribution parameters | Shane Nowell, Steven Michael Kientz, Michael Sheperek, Mustafa N. Kaynak, Kishore Kumar Muchherla +1 more | 2023-07-18 |
| 11693745 | Error-handling flows in memory devices based on bins | Shane Nowell, Steven Michael Kientz | 2023-07-04 |
| 11675509 | Multiple open block families supporting multiple cursors of a memory device | Shane Nowell, Michael Sheperek, Larry J. Koudele, Steve Kientz | 2023-06-13 |
| 11675511 | Associating multiple cursors with block family of memory device | Michael Sheperek, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz | 2023-06-13 |
| 11669380 | Dynamic programming of page margins | Michael Sheperek, Larry J. Koudele | 2023-06-06 |
| 11669398 | Memory components with ordered sweep error recovery | Gerald L. Cadloni, Francis Chew, Larry J. Koudele | 2023-06-06 |
| 11651828 | First-pass dynamic program targeting (DPT) | Michael Sheperek, Larry J. Koudele | 2023-05-16 |