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Three-dimensional field effect device |
Huimei Zhou, Shogo Mochizuki, Peng Xu, Nicolas Loubet |
2023-11-14 |
| 11810918 |
Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers |
Tsung-Sheng Kang, Ardasheir Rahman, Tao Li |
2023-11-07 |
| 11810828 |
Transistor boundary protection using reversible crosslinking reflow |
Jing Guo, Ekmini Anuja De Silva, Indira Seshadri, Jingyun Zhang |
2023-11-07 |
| 11742354 |
Top epitaxial layer and contact for VTFET |
Ruilong Xie, Christopher J. Waskiewicz, Alexander Reznicek, Heng Wu |
2023-08-29 |
| 11694958 |
Layout design for threshold voltage tuning |
Huimei Zhou, Miaomiao Wang, Zuoguang Liu |
2023-07-04 |
| 11646358 |
Sacrificial fin for contact self-alignment |
Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz, Eric R. Miller |
2023-05-09 |
| 11621199 |
Silicide formation for source/drain contact in a vertical transport field-effect transistor |
Heng Wu, Ruilong Xie, Huai Huang |
2023-04-04 |
| 11615990 |
CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor |
Heng Wu, Ruilong Xie, Jay William Strane, Hemanth Jagannathan |
2023-03-28 |
| 11605717 |
Wrapped-around contact for vertical field effect transistor top source-drain |
Ruilong Xie, Eric R. Miller, Jeffrey C. Shearer, Heng Wu |
2023-03-14 |