Issued Patents 2022
Showing 51–72 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11309240 | Conductive rail structure for semiconductor devices | Yi-Bo Liao, Wei Ju Lee, Cheng-Ting Chung, Hou-Yu Chen, Chun-Fu Cheng | 2022-04-19 |
| 11309396 | Semiconductor device and manufacturing method thereof | Wei-Hao Wu, Zhi-Chang Lin, Ting-Hung Hsu | 2022-04-19 |
| 11309212 | Semiconductor device structure and methods of forming the same | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2022-04-19 |
| 11302825 | Self-aligned spacers for multi-gate devices and method of fabrication thereof | Kuo-Cheng Ching, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang | 2022-04-12 |
| 11296081 | Integration of silicon channel nanostructures and silicon-germanium channel nanostructures | Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Guan-Lin Chen | 2022-04-05 |
| 11289583 | High aspect ratio gate structure formation | Sai-Hooi Yeong, Chi On Chui, Kai-Hsuan Lee, Chih-Hao Wang | 2022-03-29 |
| 11289606 | Capacitance reduction for back-side power rail device | Shi Ning Ju, Chih-Hao Wang, Kuo-Cheng Chiang, Wen-Ting Lan | 2022-03-29 |
| 11289141 | Integrated circuit with asymmetric arrangements of memory arrays | Xiu-Li YANG, He-Zhou WAN, Ching-Wei Wu | 2022-03-29 |
| 11282943 | Multi-gate devices and fabricating the same with etch rate modulation | Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Chung-Wei Wu +1 more | 2022-03-22 |
| 11282935 | Gate-all-around device with protective dielectric layer and method of forming the same | Cheng-Ting Chung, Yi-Bo Liao, Hou-Yu Chen | 2022-03-22 |
| 11276695 | Multi-gate device and related methods | Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang | 2022-03-15 |
| 11271094 | Semiconductor structure and method of manufacturing the same | Chi-Yi Chuang, Ching-Wei Tsai, Chih-Hao Wang | 2022-03-08 |
| 11264508 | Leakage prevention structure and method | Ching-Wei Tsai, Yi-Bo Liao, Sai-Hooi Yeong, Hou-Yu Chen, Yu-Xuan Huang | 2022-03-01 |
| 11264326 | Contact via formation | Lin-Yu Huang, Li-Zhen Yu, Chih-Hao Wang, Cheng-Chi Chuang, Chia-Hao Chang | 2022-03-01 |
| 11257903 | Method for manufacturing semiconductor structure with hybrid nanostructures | Wen-Ting Lan, Guan-Lin Chen, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang +1 more | 2022-02-22 |
| 11245029 | Structure and formation method of semiconductor device with metal gate stack | Wang-Chun Huang, Ching-Wei Tsai, Chih-Hao Wang | 2022-02-08 |
| 11239325 | Semiconductor device having backside via and method of fabricating thereof | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2022-02-01 |
| 11239208 | Packaged semiconductor devices including backside power rails and methods of forming the same | Chi-Yi Chuang, Hou-Yu Chen | 2022-02-01 |
| 11227932 | FinFET devices with a fin top hardmask | Kuo-Cheng Ching, Kai-Chieh Yang, Ching-Wei Tsai, Chih-Hao Wang | 2022-01-18 |
| 11227917 | Nano-sheet-based devices with asymmetric source and drain configurations | Cheng-Ting Chung, Yu-Xuan Huang, Yi-Bo Liao, Ching-Wei Tsai | 2022-01-18 |
| 11222958 | Negative capacitance transistor with external ferroelectric structure | Chi-Hsing Hsu, Sai-Hooi Yeong, Ching-Wei Tsai, Chih-Hao Wang, Min Cao | 2022-01-11 |
| 11217484 | FinFET gate structure and related methods | Cheng-Ting Chung, Ching-Wei Tsai | 2022-01-04 |