Issued Patents 2022
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532720 | Semiconductor device and manufacturing method thereof | Hou-Yu Chen, Ching-Wei Tsai | 2022-12-20 |
| 11532715 | Source/drain contacts for semiconductor devices and methods of forming | Ching-Wei Tsai, Yi-Bo Liao, Yu-Xuan Huang, Kuan-Lun Cheng | 2022-12-20 |
| 11532711 | PMOSFET source drain | Kuan-Lun Cheng | 2022-12-20 |
| 11532556 | Structure and method for transistors having backside power rails | Yu-Xuan Huang, Ching-Wei Tsai, Cheng-Chi Chuang, Shang-Wen Chang | 2022-12-20 |
| 11417766 | Transistors having nanostructures | Ching-Wei Tsai, Kuan-Lun Cheng | 2022-08-16 |
| 11404417 | Low leakage device | Ching-Wei Tsai, Kuan-Lun Cheng | 2022-08-02 |
| 11309240 | Conductive rail structure for semiconductor devices | Yi-Bo Liao, Wei Ju Lee, Hou-Yu Chen, Chun-Fu Cheng, Kuan-Lun Cheng | 2022-04-19 |
| 11282935 | Gate-all-around device with protective dielectric layer and method of forming the same | Yi-Bo Liao, Hou-Yu Chen, Kuan-Lun Cheng | 2022-03-22 |
| 11276637 | Barrier-free interconnect structure and manufacturing method thereof | Pei-Yu Wang, Wei Ju Lee | 2022-03-15 |
| 11251308 | Semiconductor device and method | Yi-Bo Liao, Yu-Xuan Huang, Pei-Yu Wang, Ching-Wei Tsai, Hou-Yu Chen | 2022-02-15 |
| 11227917 | Nano-sheet-based devices with asymmetric source and drain configurations | Yu-Xuan Huang, Yi-Bo Liao, Ching-Wei Tsai, Kuan-Lun Cheng | 2022-01-18 |
| 11217484 | FinFET gate structure and related methods | Ching-Wei Tsai, Kuan-Lun Cheng | 2022-01-04 |