Issued Patents 2020
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879200 | Sidewall spacer to reduce bond pad necking and/or redistribution layer necking | Alexander Kalnitsky | 2020-12-29 |
| 10868141 | Spacer structure and manufacturing method thereof | Fu-Jier Fan, Szu-Hsien Liu | 2020-12-15 |
| 10804220 | Dishing prevention columns for bipolar junction transistors | Yi-Huan Chen, Chien-Chih Chou, Meng-Han Lin | 2020-10-13 |
| 10804093 | Dishing prevention columns for bipolar junction transistors | Yi-Huan Chen, Chien-Chih Chou, Meng-Han Lin | 2020-10-13 |
| 10790279 | High voltage integration for HKMG technology | Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky +1 more | 2020-09-29 |
| 10790387 | High voltage LDMOS transistor and methods for manufacturing the same | Ker Hsiao Huo, Chien-Chih Chou, Yi-Min Chen, Chen-Liang Chu | 2020-09-29 |
| 10748899 | Epitaxial source and drain structures for high voltage devices | Yi-Huan Chen, Chien-Chih Chou | 2020-08-18 |
| 10665510 | Spacer structure and manufacturing method thereof | Alexander Kalnitsky | 2020-05-26 |
| 10658492 | Polysilicon design for replacement gate technology | Harry-Hak-Lay Chuang, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu +1 more | 2020-05-19 |
| 10658318 | Film scheme for bumping | Yao-Wen Chang, Chern-Yow Hsu, Cheng-Yuan Tsai | 2020-05-19 |
| 10629592 | Through silicon via design for stacking integrated circuits | Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu +2 more | 2020-04-21 |
| 10553583 | Boundary region for high-k-metal-gate(HKMG) integration technology | Yi-Huan Chen, Chien-Chih Chou | 2020-02-04 |
| 10535752 | Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices | Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky | 2020-01-14 |