Issued Patents 2020
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10877089 | Semiconductor wafer testing system and related method for improving external magnetic field wafer testing | Harry-Hak-Lay Chuang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang | 2020-12-29 |
| 10868250 | Resistance variable memory structure and method of forming the same | Kuo-Chi Tu, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You +2 more | 2020-12-15 |
| 10862029 | Top electrode for device structures in interconnect | Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chin-Chieh Yang, Yu-Wen Liao +2 more | 2020-12-08 |
| 10796759 | Method and apparatus for reading RRAM cell | Chin-Chieh Yang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu +4 more | 2020-10-06 |
| 10763426 | Method for forming a flat bottom electrode via (BEVA) top surface for memory | Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao +3 more | 2020-09-01 |
| 10749108 | Logic compatible RRAM structure and process | Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao | 2020-08-18 |
| 10727275 | Memory layout for reduced line loading | Wen-Ting Chu | 2020-07-28 |
| 10700275 | RRAM cell structure with laterally offset BEVA/TEVA | Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang +2 more | 2020-06-30 |
| 10680038 | RRAM memory cell with multiple filaments | Chin-Chieh Yang, Wen-Ting Chu, Yu-Wen Liao | 2020-06-09 |
| 10566387 | Interconnect landing method for RRAM technology | Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu +1 more | 2020-02-18 |
| 10566519 | Method for forming a flat bottom electrode via (BEVA) top surface for memory | Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao +3 more | 2020-02-18 |