Issued Patents 2020
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10868250 | Resistance variable memory structure and method of forming the same | Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih +2 more | 2020-12-15 |
| 10862029 | Top electrode for device structures in interconnect | Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang +2 more | 2020-12-08 |
| 10763426 | Method for forming a flat bottom electrode via (BEVA) top surface for memory | Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih +3 more | 2020-09-01 |
| 10749108 | Logic compatible RRAM structure and process | Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu | 2020-08-18 |
| 10714536 | Method to form memory cells separated by a void-free dielectric structure | Hsia-Wei Chen, Wen-Ting Chu | 2020-07-14 |
| 10700275 | RRAM cell structure with laterally offset BEVA/TEVA | Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Hsia-Wei Chen, Chin-Chieh Yang +2 more | 2020-06-30 |
| 10686125 | Memory device | Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Kuei-Hung Shen +2 more | 2020-06-16 |
| 10680038 | RRAM memory cell with multiple filaments | Chin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu | 2020-06-09 |
| 10566519 | Method for forming a flat bottom electrode via (BEVA) top surface for memory | Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih +3 more | 2020-02-18 |
| 10566387 | Interconnect landing method for RRAM technology | Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu +1 more | 2020-02-18 |
| 10529658 | Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory | Hsia-Wei Chen, Wen-Ting Chu | 2020-01-07 |