Issued Patents 2020
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10852337 | Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies | Sharad Saxena, Yuan Yu, Mike Kyu Hyon Pak, Meindert Martin Lunenborg | 2020-12-01 |
| 10854522 | Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas | Stephen Lam, Dennis Ciplickas, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2020-12-01 |
| 10777472 | IC with test structures embedded within a contiguous standard cell area | Stephen Lam, Dennis Ciplickas, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2020-09-15 |
| 10768222 | Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure | — | 2020-09-08 |
| 10643735 | Passive array test structure for cross-point memory characterization | Christopher Hess, Rakesh Vallishayee, Meindert Martin Lunenborg, Hendrik Schneider, Yuan Yu +2 more | 2020-05-05 |
| 10593604 | Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells | Stephen Lam, Dennis Ciplickas, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2020-03-17 |