Issued Patents 2020
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10830841 | Magnetic tunnel junction performance monitoring based on magnetic field coupling | Benjamin D. Briggs, Michael Rizzolo, Lawrence A. Clevenger, Theodorus E. Standaert, James H. Stathis | 2020-11-10 |
| 10796833 | Magnetic tunnel junction with low series resistance | Benjamin D. Briggs, Michael Rizzolo, Theodorus E. Standaert, Lawrence A. Clevenger, James H. Stathis | 2020-10-06 |
| 10770511 | Structures and methods for embedded magnetic random access memory (MRAM) fabrication | Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert | 2020-09-08 |
| 10746782 | Accelerated wafer testing using non-destructive and localized stress | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis | 2020-08-18 |
| 10741751 | Fully aligned semiconductor device with a skip-level via | Benjamin D. Briggs, Chih-Chao Yang, Hsueh-Chung Chen, Lawrence A. Clevenger | 2020-08-11 |
| 10739397 | Accelerated wafer testing using non-destructive and localized stress | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis | 2020-08-11 |
| 10727124 | Structure and method for forming fully-aligned trench with an up-via integration scheme | Lawrence A. Clevenger, Benjamin D. Briggs | 2020-07-28 |
| 10720567 | Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shield | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert | 2020-07-21 |
| 10553789 | Fully aligned semiconductor device with a skip-level via | Benjamin D. Briggs, Chih-Chao Yang, Hsueh-Chung Chen, Lawrence A. Clevenger | 2020-02-04 |