Issued Patents 2020
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879073 | Insulating gate separation structure for transistor devices | Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos | 2020-12-29 |
| 10879375 | Gate tie-down enablement with inner spacer | Su Chen Fan, Lars Liebmann, Sanjay C. Mehta | 2020-12-29 |
| 10832944 | Interconnect structure having reduced resistance variation and method of forming same | Nicholas V. LiCausi, Chanro Park, Ruilong Xie | 2020-11-10 |
| 10832961 | Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor | Su Chen Fan, Ruilong Xie, Veeraraghavan S. Basker, Chanro Park | 2020-11-10 |
| 10790376 | Contact structures | Ruilong Xie, Chanro Park, Julien Frougier, Kangguo Cheng | 2020-09-29 |
| 10770585 | Self-aligned buried contact for vertical field-effect transistor and method of production thereof | Ruilong Xie, Chanro Park, Daniel Chanemougame | 2020-09-08 |
| 10566201 | Gate cut method after source/drain metallization | Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos | 2020-02-18 |