Issued Patents 2020
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10877068 | High density and fine pitch interconnect structures in an electric test apparatus | Pooya Tadayon, Joe Walczyk | 2020-12-29 |
| 10790354 | Self-aligned gate edge and local interconnect | Milton Clair Webb, Tahir Ghani, Szuya S. Liao | 2020-09-29 |
| 10770587 | Semiconductor device having tipless epitaxial source/drain regions | — | 2020-09-08 |
| 10685947 | Distributed semiconductor die and package architecture | Wilfred Gomes, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. Mc Cullough | 2020-06-16 |
| 10672650 | Via blocking layer | Rami Hourani, Marie Krysak, Florian Gstrein, Ruth A. Brain | 2020-06-02 |
| 10629483 | Self-aligned contacts | Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2020-04-21 |
| 10535601 | Via blocking layer | Rami Hourani, Marie Krysak, Florian Gstrein, Ruth A. Brain, Manish Chandhok | 2020-01-14 |