Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515823 | Via connection to a partially filled trench | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee +1 more | 2019-12-24 |
| 10510657 | Semiconductor device with interconnecting structure and method for manufacturing the same | Shin-Yi Yang, Ming-Han Lee | 2019-12-17 |
| 10490497 | Selective formation of conductor nanowires | Chao-Hsien Peng, Hsiang-Huan Lee | 2019-11-26 |
| 10319632 | Semiconductor interconnect structure having a graphene barrier layer | Shin-Yi Yang, Ming-Han Lee | 2019-06-11 |
| 10312139 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao | 2019-06-04 |
| 10269915 | Vertical MOS transistor and fabricating method thereof | Tai-I Yang, Yung-Chih Wang, Shin-Yi Yang, Chih Wei Lu, Hsin-Ping Chen | 2019-04-23 |
| 10269706 | Semiconductor device and manufacturing method thereof | Ming-Han Lee | 2019-04-23 |
| 10269634 | Semiconductor device having voids and method of forming same | Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao | 2019-04-23 |
| 10170306 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Chung-Ju Lee, Hsin-Chieh Yao, Tien-I Bao, Yung-Hsu Wu | 2019-01-01 |