Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522654 | Gate tie-down enablement with inner spacer | Su Chen Fan, Lars Liebmann, Sanjay C. Mehta | 2019-12-31 |
| 10468300 | Contacting source and drain of a transistor device | Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Chanro Park, Nigel G. Cave +1 more | 2019-11-05 |
| 10388602 | Local interconnect structure including non-eroded contact via trenches | Su Chen Fan, Vimal Kamineni, Ruilong Xie | 2019-08-20 |
| 10332977 | Gate tie-down enablement with inner spacer | Su Chen Fan, Lars Liebmann, Sanjay C. Mehta | 2019-06-25 |
| 10283408 | Middle of the line (MOL) contacts with two-dimensional self-alignment | Ruilong Xie, Chanro Park, Lars Liebmann | 2019-05-07 |
| 10249728 | Air-gap gate sidewall spacer and method | Daniel Chanemougame, Ruilong Xie, Lars Liebmann, Nigel G. Cave, Guillaume Bouche | 2019-04-02 |
| 10243053 | Gate contact structure positioned above an active region of a transistor device | Ruilong Xie, Chanro Park | 2019-03-26 |
| 10211100 | Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistor | Ruilong Xie, Lars Liebmann, Nigel G. Cave, Nicholas V. LiCausi, Guillaume Bouche +1 more | 2019-02-19 |
| 10204994 | Methods of forming a semiconductor device with a gate contact positioned above the active region | Ruilong Xie, Chanro Park, Lars Liebmann, Nigel G. Cave, Mark V. Raymond +2 more | 2019-02-12 |