Issued Patents 2019
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10521003 | Method and apparatus to shutdown a memory channel | Murugasamy K. Nachimuthu | 2019-12-31 |
| 10514931 | Computing platform interface with memory management | Sarathy Jayakumar, Neelam Chandwani | 2019-12-24 |
| 10503587 | Scrubbing disaggregated storage | Anjaneya Reddy Chagam Reddy, Sujoy Sen, Tushar Gohad | 2019-12-10 |
| 10498604 | Capability determination for computing resource allocation | Mrittika Ganguli, Jaiber J. John, Tessil Thomas | 2019-12-03 |
| 10489156 | Techniques to verify and authenticate resources in a data center computer environment | Alberto J. Munoz, Murugasamy K. Nachimuthu, Wojciech Stefan Powiertowski, Sergiu D. Ghetie, Neeraj Upasani +3 more | 2019-11-26 |
| 10474596 | Providing dedicated resources for a system management mode of a processor | Sarathy Jayakumar, Ashok Raj, John G. Holm, Narayan Ranganathan, Sergiu D. Ghetie | 2019-11-12 |
| 10445154 | Firmware-related event notification | Sarathy Jayakumar, Vincent J. Zimmer, Rajesh Poornachandran | 2019-10-15 |
| 10423559 | System for selectively upgradeable disaggregated server components | Sheshaprasad G. Krishnapura, Vipul Lal, Shaji Kootaal Achuthan, Ty H. Tang | 2019-09-24 |
| 10417070 | Techniques for handling errors in persistent memory | Murugasamy K. Nachimuthu, Camille C. Raad | 2019-09-17 |
| 10387072 | Systems and method for dynamic address based mirroring | Sarathy Jayakumar, Ashok Raj, Hemalatha Gurumoorthy, Ronald N. Story | 2019-08-20 |
| 10368148 | Configurable computing resource physical location determination | Murugasamy K. Nachimuthu | 2019-07-30 |
| 10359940 | Method and apparatus for dynamically allocating storage resources to compute nodes | Mark A. Schmisseur, Balint Fleischer, Debendra Das Sharma, Raj K. Ramanujan | 2019-07-23 |
| 10331614 | Method and apparatus for server platform architectures that enable serviceable nonvolatile memory modules | Dimitrios Ziakas, Bassam N. Coury, Murugasamy K. Nachimuthu, Thi Dang, Russell J. Wunderlich | 2019-06-25 |
| 10324852 | System and method to increase availability in a multi-level memory configuration | Theodros Yigzaw, Ashok Raj, Robert C. Swanson | 2019-06-18 |
| 10319458 | Hardware apparatuses and methods to check data storage devices for transient faults | Ashok Raj, Ron Gabor, Hisham Shafi, Theodros Yigzaw | 2019-06-11 |
| 10296416 | Read from memory instructions, processors, methods, and systems, that do not take exception on defective data | Ashok Raj, Ron Gabor, Hisham Shafi, Sergiu D. Ghetie, Theodros Yigzaw +2 more | 2019-05-21 |
| 10296399 | Data coherency model and protocol at cluster level | Debendra Das Sharma, Balint Fleischer | 2019-05-21 |
| 10277677 | Mechanism for disaggregated storage class memory over fabric | Murugasamy K. Nachimuthu | 2019-04-30 |
| 10241912 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2019-03-26 |
| 10229065 | Unified hardware and software two-level memory | Murugasamy K. Nachimuthu | 2019-03-12 |
| 10229024 | Assisted coherent shared memory | Debendra Das Sharma, Balint Fleischer | 2019-03-12 |
| 10223187 | Instruction and logic to expose error domain topology to facilitate failure isolation in a processor | Ashok Raj, Narayan Ranganathan, Vincent J. Zimmer | 2019-03-05 |
| 10223204 | Apparatus and method for detecting and recovering from data fetch errors | Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati Srinivasa, Jose A. Vargas, Hisham Shafi +5 more | 2019-03-05 |
| 10185619 | Handling of error prone cache line slots of memory side cache of multi-level system memory | Theodros Yigzaw, Ashok Raj, Robert C. Swanson | 2019-01-22 |
| 10176108 | Accessing memory coupled to a target node from an initiator node | Murugasamy K. Nachimuthu, Dimitrios Ziakas | 2019-01-08 |