Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10474596 | Providing dedicated resources for a system management mode of a processor | Sarathy Jayakumar, John G. Holm, Narayan Ranganathan, Mohan J. Kumar, Sergiu D. Ghetie | 2019-11-12 |
| 10430267 | Determine when an error log was created | Narayan Ranganathan | 2019-10-01 |
| 10387072 | Systems and method for dynamic address based mirroring | Sarathy Jayakumar, Mohan J. Kumar, Hemalatha Gurumoorthy, Ronald N. Story | 2019-08-20 |
| 10324852 | System and method to increase availability in a multi-level memory configuration | Theodros Yigzaw, Robert C. Swanson, Mohan J. Kumar | 2019-06-18 |
| 10319458 | Hardware apparatuses and methods to check data storage devices for transient faults | Ron Gabor, Hisham Shafi, Mohan J. Kumar, Theodros Yigzaw | 2019-06-11 |
| 10318368 | Enabling error status and reporting in a machine check architecture | Theodros Yigzaw | 2019-06-11 |
| 10296416 | Read from memory instructions, processors, methods, and systems, that do not take exception on defective data | Ron Gabor, Hisham Shafi, Sergiu D. Ghetie, Mohan J. Kumar, Theodros Yigzaw +2 more | 2019-05-21 |
| 10223187 | Instruction and logic to expose error domain topology to facilitate failure isolation in a processor | Narayan Ranganathan, Mohan J. Kumar, Vincent J. Zimmer | 2019-03-05 |
| 10185619 | Handling of error prone cache line slots of memory side cache of multi-level system memory | Theodros Yigzaw, Robert C. Swanson, Mohan J. Kumar | 2019-01-22 |