Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10460971 | Multi-chip package assembly | — | 2019-10-29 |
| 10431847 | Stacked film battery architecture | Kuniaki Sueoka | 2019-10-01 |
| 10424510 | Solder fill into high aspect through holes | Toyohiro Aoki, Kuniaki Sueoka, Kazushige Toriyama | 2019-09-24 |
| 10388566 | Solder fill into high aspect through holes | Toyohiro Aoki, Kuniaki Sueoka, Kazushige Toriyama | 2019-08-20 |
| 10388578 | Wafer scale testing and initialization of small die chips | Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka | 2019-08-20 |
| 10325839 | Reduction of stress in via structure | Toyohiro Aoki, Takashi Hisada, Sayuri Hada, Eiji Nakamura, Kuniaki Sueoka | 2019-06-18 |
| 10317625 | Polymer waveguide (PWG) connector assembly having both cores and cladding partially exposed | Hidetoshi Numata | 2019-06-11 |
| 10302868 | Polymer waveguide connector assembly method using cores and cladding that are both partially exposed | Hidetoshi Numata | 2019-05-28 |
| 10252363 | Forming a solder joint between metal layers | Toyohiro Aoki, Hiroyuki Mori, Yasumitsu Orii, Kazushige Toriyama, Ting-Li Yang | 2019-04-09 |
| 10170443 | Debonding chips from wafer | — | 2019-01-01 |