Issued Patents 2018
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10128352 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Sanjay C. Mehta | 2018-11-13 |
| 10090193 | Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and method | Daniel Chanemougame, Ruilong Xie | 2018-10-02 |
| 10079173 | Methods of forming metallization lines on integrated circuit products and the resulting products | Ruilong Xie, Daniel Chanemougame, Geng Han | 2018-09-18 |
| 10074564 | Self-aligned middle of the line (MOL) contacts | Daniel Chanemougame, Ruilong Xie | 2018-09-11 |
| 10042969 | Reliability of an electronic device | Rasit Onur Topaloglu | 2018-08-07 |
| 10026824 | Air-gap gate sidewall spacer and method | Daniel Chanemougame, Andre P. Labonte, Ruilong Xie, Nigel G. Cave, Guillaume Bouche | 2018-07-17 |
| 9978608 | Fin patterning for a fin-type field-effect transistor | Ruilong Xie, Min Gyu Sung, Nigel G. Cave | 2018-05-22 |
| 9947589 | Methods of forming a gate contact for a transistor above an active region and the resulting device | Chanro Park, Ruilong Xie, Andre P. Labonte, Nigel G. Cave, Mark V. Raymond | 2018-04-17 |
| 9941162 | Self-aligned middle of the line (MOL) contacts | Daniel Chanemougame, Ruilong Xie | 2018-04-10 |
| 9941163 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Sanjay C. Mehta | 2018-04-10 |
| 9929157 | Tall single-fin fin-type field effect transistor structures and methods | Ruilong Xie, Andreas Knorr, Murat Kerem Akarvardar, Nigel G. Cave | 2018-03-27 |
| 9929049 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Sanjay C. Mehta | 2018-03-27 |
| 9929048 | Middle of the line (MOL) contacts with two-dimensional self-alignment | Ruilong Xie, Chanro Park, Andre P. Labonte | 2018-03-27 |
| 9911619 | Fin cut with alternating two color fin hardmask | Ruilong Xie, Hoon Kim, Catherine B. Labelle, Chanro Park, Min Gyu Sung | 2018-03-06 |
| 9899259 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Sanjay C. Mehta | 2018-02-20 |