Issued Patents 2017
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847253 | Package-on-package using through-hole via die on saw streets | Heap Hoe Kuan, Seng Guan Chow | 2017-12-19 |
| 9824975 | Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die | Reza A. Pagaila, Linda Pei Ee Chua | 2017-11-21 |
| 9799589 | Integrated circuit packaging system with a grid array with a leadframe and method of manufacture thereof | Arnel Senosa Trasporto, Linda Pei Ee Chua | 2017-10-24 |
| 9679881 | Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material | Reza A. Pagaila, Linda Pei Ee Chua | 2017-06-13 |
| 9640504 | Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core | Reza A. Pagaila, Shuangwu Huang | 2017-05-02 |
| 9620480 | Integrated circuit packaging system with unplated leadframe and method of manufacture thereof | Garret Dimaculangan, Linda Pei Ee Chua, Arnel Senosa Trasporto | 2017-04-11 |
| 9601369 | Semiconductor device and method of forming conductive vias with trench in saw street | Reza A. Pagaila | 2017-03-21 |
| 9583446 | Semiconductor device and method of forming a shielding layer between stacked semiconductor die | Reza A. Pagaila, Nathapong Suthiwongsunthorn | 2017-02-28 |
| 9576873 | Integrated circuit packaging system with routable trace and method of manufacture thereof | Arnel Senosa Trasporto, Linda Pei Ee Chua | 2017-02-21 |