Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9778316 | Multi-stage test response compactors | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab | 2017-10-03 |
| 9720038 | Method and circuit of pulse-vanishing test | Shi-Yu Huang, Kun-Han Tsai, Jeo-Yen Lee | 2017-08-01 |
| 9689918 | Test access architecture for stacked memory and logic dies | Ruifeng Guo, Yu Huang, Liyang Lai, Etienne Racine, Martin Keim +3 more | 2017-06-27 |
| 9626474 | Expanded canonical forms of layout patterns | — | 2017-04-18 |