Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9778316 | Multi-stage test response compactors | Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng | 2017-10-03 |
| 9720040 | Timing-aware test generation and fault simulation | Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang | 2017-08-01 |
| 9720041 | Scan-based test architecture for interconnects in stacked designs | Jerzy Tyszer | 2017-08-01 |
| 9714981 | Test-per-clock based on dynamically-partitioned reconfigurable scan chains | Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski | 2017-07-25 |
| 9651622 | Isometric test compression with low toggling activity | Amit Amar Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Jerzy Tyszer +1 more | 2017-05-16 |
| 9568552 | Logic built-in self-test with high test coverage and low switching activity | Xijiang Lin | 2017-02-14 |