Issued Patents 2016
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9525040 | Method of fabricating hybrid impact-ionization semiconductor device | Ming Zhu, Lee-Wee Teo | 2016-12-20 |
| 9515069 | Semiconductor die | Ming Zhu | 2016-12-06 |
| 9508721 | Metal gate structure of a CMOS semiconductor device | Ming Zhu, Bao-Ru Young | 2016-11-29 |
| 9502533 | Silicon recess etch and epitaxial deposit for shallow trench isolation (STI) | Bao-Ru Young, Wei-Cheng Wu, Kong-Pin Chang, Chia Ming Liang, Meng-Fang Hsu +2 more | 2016-11-22 |
| 9502514 | Memory devices and method of forming same | Chang-Ming Wu, Wei-Cheng Wu, Shih-Chang Liu, Chia-Shiung Tsai | 2016-11-22 |
| 9502466 | Dummy bottom electrode in interconnect to reduce CMP dishing | Wen-Chun You | 2016-11-22 |
| 9496276 | CMP fabrication solution for split gate memory embedded in HK-MG process | Wei-Cheng Wu, Chang-Ming Wu, Shih-Chang Liu | 2016-11-15 |
| 9484352 | Method for forming a split-gate flash memory cell device with a low power logic device | Chang-Ming Wu, Shih-Chang Liu | 2016-11-01 |
| 9484351 | Split gate memory device and method of fabricating the same | Chang-Ming Wu, Wei-Cheng Wu, Shih-Chang Liu, Chia-Shiung Tsai | 2016-11-01 |
| 9478633 | Method and apparatus of forming ESD protection device | Ming Zhu, Lee-Wee Teo | 2016-10-25 |
| 9472636 | Cost-effective gate replacement process | Ming Zhu, Bao-Ru Young, Jyun-Ming Lin, Wei-Cheng Wu | 2016-10-18 |
| 9466714 | Vertical tunneling field-effect transistor cell with coaxially arranged gate contacts and drain contacts | Cheng-Cheng Kuo, Ming Zhu | 2016-10-11 |
| 9455344 | Integrated circuit metal gate structure having tapered profile | Kong-Beng Thei, Chiung-Han Yeh, Ming-Yuan Wu, Mong-Song Liang | 2016-09-27 |
| 9431500 | Integrated circuit device having defined gate spacing and method of designing and fabricating thereof | Ming Zhu, Po-Nien Chen, Bao-Ru Young | 2016-08-30 |
| 9431413 | STI recess method to embed NVM memory in HKMG replacement gate technology | Wei-Cheng Wu, Ya-Chen Kao | 2016-08-30 |
| 9425206 | Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology | Wei-Cheng Wu, Ya-Chen Kao, Shih-Chang Liu, Fang-Lan Chu | 2016-08-23 |
| 9419099 | Method of fabricating spacers in a strained semiconductor device | Chen-Pin Hsu, Kong-Beng Thei | 2016-08-16 |
| 9412841 | Method of fabricating a transistor using contact etch stop layers | Lee-Wee Teo, Ming Zhu, Bao-Ru Young | 2016-08-09 |
| 9406669 | Method and structure for vertical tunneling field effect transistor and planar devices | Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu | 2016-08-02 |
| 9397112 | L-shaped capacitor in thin film storage technology | Wei-Cheng Wu, Chien-Hung Chang | 2016-07-19 |
| 9390927 | Contact formation for split gate flash memory | Wei-Cheng Wu, Ya-Chen Kao, Chin-Yi Huang | 2016-07-12 |
| 9378961 | Methods of fabricating multiple gate stack compositions | Po-Nien Chen, Bao-Ru Young, Chi-Hsun Hsieh, Wei-Cheng Wu, Eric Huang | 2016-06-28 |
| 9368603 | Contact for high-k metal gate device | Huan-Just Lin | 2016-06-14 |
| 9355209 | Revising layout design through OPC to reduce corner rounding effect | Cheng-Cheng Kuo, Ching-Che Tsai, Bao-Ru Young | 2016-05-31 |
| 9349655 | Method for mechanical stress enhancement in semiconductor devices | Carlos H. Diaz, Yi-Ming Sheu, Anson Wang, Kong-Beng Thei, Sheng-Chen Chung +3 more | 2016-05-24 |