Issued Patents 2016
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9520498 | FinFET structure and method for fabricating the same | Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang | 2016-12-13 |
| 9520446 | Innovative approach of 4F2 driver formation for high-density RRAM and MRAM | Yu-Wei Ting, Chun-Yang Tsai, Kuo-Ching Huang | 2016-12-13 |
| 9508603 | Formation of nickel silicon and nickel germanium structure at staggered times | Chao-Hsiung Wang | 2016-11-29 |
| 9496397 | FinFet device with channel epitaxial region | Kuo-Cheng Ching, Zhi-Chang Lin, Chao-Hsiung Wang | 2016-11-15 |
| 9461110 | FETs and methods of forming FETs | Chih-Hao Wang, Ching-Wei Tsai, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien | 2016-10-04 |
| 9455334 | Method of forming a Fin structure of semiconductor device | Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang | 2016-09-27 |
| 9449975 | FinFET devices and methods of forming | Kuo-Cheng Ching | 2016-09-20 |
| 9418897 | Wrap around silicide for FinFETs | Kuo-Cheng Ching, Ying-Keung Leung | 2016-08-16 |
| 9406669 | Method and structure for vertical tunneling field effect transistor and planar devices | Harry-Hak-Lay Chuang, Yi-Ren Chen, Chao-Hsiung Wang, Ming Zhu | 2016-08-02 |
| 9397159 | Silicide region of gate-all-around transistor | Kuo-Cheng Ching, Chao-Hsiung Wang | 2016-07-19 |
| 9385234 | FinFETs with strained well regions | Yi-Jing Lee | 2016-07-05 |
| 9385069 | Gate contact structure for FinFET | Chao-Hsiung Wang | 2016-07-05 |
| 9379108 | Contact structure of semiconductor device | Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Li-Chi Yu, Meng-Chun Chang +2 more | 2016-06-28 |
| 9362386 | FETs and methods for forming the same | Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee | 2016-06-07 |
| 9349841 | FinFETs and methods for forming the same | Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi Kang Liu, Yung-Ta Li +2 more | 2016-05-24 |
| 9337318 | FinFET with dummy gate on non-recessed shallow trench isolation (STI) | Chao-Hsiung Wang | 2016-05-10 |
| 9337303 | Metal gate stack having TiAICN as work function layer and/or blocking/wetting layer | Shiu-Ko JangJian, Chi-Cherng Jeng, Ting-Chun Wang | 2016-05-10 |
| 9337263 | Semiconductor device including a semiconductor sheet unit interconnecting a source and a drain | Jiun-Peng Wu, Tetsu Ohtou, Ching-Wei Tsai, Chih-Hao Wang | 2016-05-10 |
| 9337192 | Metal gate stack having TaAlCN layer | Shiu-Ko JangJian, Ting-Chun Wang, Chi-Cherng Jeng | 2016-05-10 |
| 9331075 | Systems and methods for fabricating semiconductor devices at different levels | Chao-Hsiung Wang | 2016-05-03 |
| 9331179 | Metal gate and gate contact structure for FinFET | Chao-Hsiung Wang | 2016-05-03 |
| 9318431 | Integrated circuit having a MOM capacitor and method of making same | Chao-Hsiung Wang | 2016-04-19 |
| 9318367 | FinFET structure with different fin heights and method for forming the same | Yu-Lien Huang, Chi Kang Liu | 2016-04-19 |
| 9312354 | Contact etch stop layers of a field effect transistor | Chao-Hsiung Wang | 2016-04-12 |
| 9312363 | Multi-fin device and method of making same | Chao-Hsiung Wang | 2016-04-12 |