Issued Patents 2016
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9502585 | Schottky barrier diode and method of manufacturing the same | Meng-Han Lin, Chien-Chih Chou, Chih-Wen Hsiung | 2016-11-22 |
| 9455344 | Integrated circuit metal gate structure having tapered profile | Harry-Hak-Lay Chuang, Chiung-Han Yeh, Ming-Yuan Wu, Mong-Song Liang | 2016-09-27 |
| 9437494 | Semiconductor arrangement and formation thereof | Alexander Kalnitsky, Chien-Chih Chou, Chen-Liang Chu, Hsiao-Chin Tuan | 2016-09-06 |
| 9419099 | Method of fabricating spacers in a strained semiconductor device | Chen-Pin Hsu, Harry-Hak-Lay Chuang | 2016-08-16 |
| 9362272 | Lateral MOSFET | Huei-Ru Liu, Chien-Chih Chou | 2016-06-07 |
| 9356108 | Dummy structure for multiple gate dielectric interface and methods | Huei-Ru Liou, Chien-Chih Chou, Gwo-Yuh Shiau | 2016-05-31 |
| 9349655 | Method for mechanical stress enhancement in semiconductor devices | Carlos H. Diaz, Yi-Ming Sheu, Anson Wang, Sheng-Chen Chung, Hao-Yi Tsai +3 more | 2016-05-24 |
| 9318366 | Method of forming integrated circuit having modified isolation structure | Chien-Chih Chou | 2016-04-19 |
| 9299806 | High voltage drain-extended MOSFET having extra drain-OD addition | Yi-Sheng Chen, Chen-Liang Chu, Shih-Kuang Hsiao, Fei-Yuh Chen | 2016-03-29 |
| 9263396 | Photo alignment mark for a gate last process | Chun-Liang Shen, Ming-Yuan Wu, Chiung-Han Yeh, Harry-Hak-Lay Chuang | 2016-02-16 |