| 9530860 |
III-V MOSFETs with halo-doped bottom barrier layer |
Pranita Kerber, Chung-Hsun Lin, Jeffrey W. Sleight |
2016-12-27 |
| 9515165 |
III-V field effect transistor (FET) with reduced short channel leakage, integrated circuit (IC) chip and method of manufacture |
Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung |
2016-12-06 |
| 9508640 |
Multiple via structure and method |
Cheng-Wei Cheng, Szu-Lin Cheng, Keith E. Fogel, Edward W. Kiewra, Devendra K. Sadana +2 more |
2016-11-29 |
| 9502562 |
Fin field effect transistor including self-aligned raised active regions |
Anirban Basu, Guy M. Cohen |
2016-11-22 |
| 9496347 |
Graded buffer epitaxy in aspect ratio trapping |
Cheng-Wei Cheng, Kuen-Ting Shiu, Jeng-Bang Yau |
2016-11-15 |
| 9484463 |
Fabrication process for mitigating external resistance of a multigate device |
Anirban Basu, Guy M. Cohen |
2016-11-01 |
| 9472658 |
III-V nanowire FET with compositionally-graded channel and wide-bandgap core |
Anirban Basu, Guy M. Cohen, Jeffrey W. Sleight |
2016-10-18 |
| 9472667 |
III-V MOSFET with strained channel and semi-insulating bottom barrier |
Anirban Basu, Guy M. Cohen |
2016-10-18 |
| 9437613 |
Multiple VT in III-V FETs |
Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight |
2016-09-06 |
| 9431494 |
Low interfacial defect field effect transistor |
Anirban Basu, Guy M. Cohen |
2016-08-30 |
| 9397226 |
Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts |
Anirban Basu, Cheng-Wei Cheng, Wilfried E. Haensch, Kuen-Ting Shiu |
2016-07-19 |
| 9385180 |
Semiconductor device structures and methods of forming semiconductor structures |
Justin K. Brask, Jack T. Kavalieros, Brian S. Doyle, Uday Shah, Suman Datta +1 more |
2016-07-05 |
| 9368574 |
Nanowire field effect transistor with inner and outer gates |
Anirban Basu, Guy M. Cohen, Jeffrey W. Sleight |
2016-06-14 |
| 9343142 |
Nanowire floating gate transistor |
Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight |
2016-05-17 |
| 9337309 |
Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels |
Anirban Basu, Jeffrey W. Sleight |
2016-05-10 |
| 9337307 |
Method for fabricating transistor with thinned channel |
Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle +3 more |
2016-05-10 |
| 9337255 |
Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels |
Anirban Basu, Jeffrey W. Sleight |
2016-05-10 |
| 9324853 |
III-V semiconductor device having self-aligned contacts |
Anirban Basu, Kuen-Ting Shiu, Yanning Sun |
2016-04-26 |
| 9299615 |
Multiple VT in III-V FETs |
Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight |
2016-03-29 |
| 9287115 |
Planar III-V field effect transistor (FET) on dielectric layer |
Cheng-Wei Cheng, Edward W. Kiewra, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu +1 more |
2016-03-15 |
| 9287362 |
Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts |
Anirban Basu, Cheng-Wei Cheng, Wilfried E. Haensch, Kuen-Ting Shiu |
2016-03-15 |
| 9287360 |
III-V nanowire FET with compositionally-graded channel and wide-bandgap core |
Anirban Basu, Guy M. Cohen, Jeffrey W. Sleight |
2016-03-15 |
| 9263260 |
Nanowire field effect transistor with inner and outer gates |
Anirban Basu, Guy M. Cohen, Jeffrey W. Sleight |
2016-02-16 |
