Issued Patents 2005
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6960523 | Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device | Michael Maldei, Prakash Dev, David M. Dobuzinsky, Johnathan E. Faltermeier, Thomas Rupp +3 more | 2005-11-01 |
| 6890815 | Reduced cap layer erosion for borderless contacts | Johnathan E. Faltermeier, Jeremy K. Stephens, David M. Dobuzinsky, Larry Clevenger, Munir D. Naeem +3 more | 2005-05-10 |
| 6884734 | Vapor phase etch trim structure with top etch blocking layer | Frederick Buehrer, Derek Chen, William Chu, Scott W. Crowder, Sadanand V. Deshpande +4 more | 2005-04-26 |
| 6864041 | Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching | Jeffrey J. Brown, Sadanand V. Deshpande, David V. Horak, Maheswaran Surendra, Len Yuan Tsou +2 more | 2005-03-08 |