Issued Patents 2003
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6602798 | Method and apparatus for reducing isolation stress in integrated circuits | Randhir P. S. Thakur, Kevin G. Donohoe, Zhiqiang Wu | 2003-08-05 |
| 6602653 | Conductive material patterning methods | Joseph E. Geusic | 2003-08-05 |
| 6599800 | Methods of forming capacitors, and methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions | Tyler Lowrey, Luan C. Tran, Mark Durcan | 2003-07-29 |
| 6600190 | Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions | Tyler Lowrey, Luan C. Tran, D. Mark Durcan | 2003-07-29 |
| 6599840 | Material removal method for forming a structure | Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan +1 more | 2003-07-29 |
| 6596642 | Material removal method for forming a structure | Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan +1 more | 2003-07-22 |
| 6596648 | Material removal method for forming a structure | Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan +1 more | 2003-07-22 |
| 6580154 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction | Wendell P. Noble, Leonard Forbes | 2003-06-17 |
| 6579803 | Removal of copper oxides from integrated interconnects | Joseph E. Geusic | 2003-06-17 |
| 6551876 | Processing methods of forming an electrically conductive plug to a node location | — | 2003-04-22 |
| 6548397 | Electrical and thermal contact for use in semiconductor devices | — | 2003-04-15 |
| 6548872 | Integrated circuitry comprising multiple transistors with different channel lengths | — | 2003-04-15 |
| 6509626 | Conductive device components of different base widths formed from a common conductive layer | — | 2003-01-21 |