Issued Patents 2003
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6638807 | Technique for gated lateral bipolar transistors | Leonard Forbes | 2003-10-28 |
| 6633067 | Compact SOI body contact link | — | 2003-10-14 |
| 6624033 | Trench DRAM cell with vertical device and buried word lines | — | 2003-09-23 |
| 6624021 | Method for forming gate segments for an integrated circuit | — | 2003-09-23 |
| 6610566 | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor | Leonard Forbes | 2003-08-26 |
| 6597037 | Programmable memory address decode array with vertical transistors | Leonard Forbes | 2003-07-22 |
| 6589851 | Semiconductor processing methods of forming a conductive grid | — | 2003-07-08 |
| 6580154 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction | Leonard Forbes, Alan R. Reinberg | 2003-06-17 |
| 6573169 | Highly conductive composite polysilicon gate for CMOS integrated circuits | Leonard Forbes | 2003-06-03 |
| 6552435 | Integrated circuit with conductive lines disposed within isolation regions | — | 2003-04-22 |
| 6545297 | High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown | Leonard Forbes | 2003-04-08 |
| 6537871 | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor | Leonard Forbes | 2003-03-25 |
| 6528837 | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor | Leonard Forbes | 2003-03-04 |
| 6521958 | MOSFET technology for programmable address decode and correction | Leonard Forbes, Eugene H. Cloud | 2003-02-18 |
| 6515510 | Programmable logic array with vertical transistors | Leonard Forbes | 2003-02-04 |
| 6509213 | Methods of forming transistors and connections thereto | — | 2003-01-21 |
| 6504201 | Memory cell having a vertical transistor with buried source/drain and dual gates | Leonard Forbes, Kie Y. Ahn | 2003-01-07 |
| 6503790 | High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown | Leonard Forbes | 2003-01-07 |