Issued Patents 2003
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670248 | Triple gate oxide process with high-k gate dielectric | Chew Hoe Ang, Wenhe Lin | 2003-12-30 |
| 6664156 | Method for forming L-shaped spacers with precise width control | Chew Hoe Ang, Eng Hua Lim, Wenhe Lin | 2003-12-16 |
| 6664153 | Method to fabricate a single gate with dual work-functions | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2003-12-16 |
| 6632712 | Method of fabricating variable length vertical transistors | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2003-10-14 |
| 6610575 | Forming dual gate oxide thickness on vertical transistors by ion implantation | Chew Hoe Ang, Eng Hua Lim, Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2003-08-26 |
| 6610604 | Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2003-08-26 |
| 6608362 | Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components | Shao Kai, Sanford Chu, Chit Hwei Ng, Sia Choon Beng, Chew Kok Wai | 2003-08-19 |
| 6605501 | Method of fabricating CMOS device with dual gate electrode | Chew Hoe Ang, Eng Hua Lim, Cher Liang Cha, Elgin Quek, Mei Sheng Zhou | 2003-08-12 |
| 6586314 | Method of forming shallow trench isolation regions with improved corner rounding | Soh Yun Siah, Liang-Choo Hsia, Chew Hoe Ang | 2003-07-01 |
| 6566208 | Method to form elevated source/drain using poly spacer | Yang Pan, Lee Yong Meng, Leung Keung, Yelehanka Ramachandramurthy Pradeep, Lap Chan +2 more | 2003-05-20 |
| 6544848 | Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2003-04-08 |
| 6544824 | Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel | Yelehanka Ramachandramurthy Pradeep, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2003-04-08 |
| 6541327 | Method to form self-aligned source/drain CMOS device on insulated staircase oxide | Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2003-04-01 |
| 6511884 | Method to form and/or isolate vertical transistors | Elgin Quek, Ravi Sundaresan, Yang Pan, Yong Meng Lee, Ying-Keung Leung +2 more | 2003-01-28 |