Issued Patents 2003
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6638844 | Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill | Purakh Raj Verma, Sanford Chu, Chit Hwei | 2003-10-28 |
| 6566208 | Method to form elevated source/drain using poly spacer | Yang Pan, Lee Yong Meng, Leung Keung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng +2 more | 2003-05-20 |
| 6566209 | Method to form shallow junction transistors while eliminating shorts due to junction spiking | Cher Liang Cha, Ravishankar Sundaresan | 2003-05-20 |
| 6566215 | Method of fabricating short channel MOS transistors with source/drain extensions | Yung Fu Chong | 2003-05-20 |
| 6566650 | Incorporation of dielectric layer onto SThM tips for direct thermal analysis | Chang Chaun Hu, Kin Leong Pey, Yung Fu Chong, Chim Wai Kin, Pavel Neuzil | 2003-05-20 |
| 6544824 | Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel | Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2003-04-08 |
| 6541327 | Method to form self-aligned source/drain CMOS device on insulated staircase oxide | Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2003-04-01 |
| 6531750 | Shallow junction transistors which eliminating shorts due to junction spiking | Cher Liang Cha, Ravishankar Sundaresan | 2003-03-11 |
| 6511884 | Method to form and/or isolate vertical transistors | Elgin Quek, Ravi Sundaresan, Yang Pan, Yong Meng Lee, Ying-Keung Leung +2 more | 2003-01-28 |