Issued Patents 2003
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670248 | Triple gate oxide process with high-k gate dielectric | Wenhe Lin, Jia Zhen Zheng | 2003-12-30 |
| 6664153 | Method to fabricate a single gate with dual work-functions | Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2003-12-16 |
| 6664156 | Method for forming L-shaped spacers with precise width control | Eng Hua Lim, Wenhe Lin, Jia Zhen Zheng | 2003-12-16 |
| 6632712 | Method of fabricating variable length vertical transistors | Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2003-10-14 |
| 6610604 | Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask | Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2003-08-26 |
| 6610575 | Forming dual gate oxide thickness on vertical transistors by ion implantation | Eng Hua Lim, Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2003-08-26 |
| 6605501 | Method of fabricating CMOS device with dual gate electrode | Eng Hua Lim, Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou | 2003-08-12 |
| 6586314 | Method of forming shallow trench isolation regions with improved corner rounding | Soh Yun Siah, Liang-Choo Hsia, Jia Zhen Zheng | 2003-07-01 |
| 6544848 | Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers | Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou +1 more | 2003-04-08 |