Issued Patents 2003
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6656840 | Method for forming silicon containing layers on a substrate | Nagarajan Rajagopalan, Joe Feng, Christopher S. Ngai, Meiyee Shek, Linh Thanh | 2003-12-02 |
| 6594540 | Misalignment tolerant techniques for dual damascene fabrication | — | 2003-07-15 |
| 6514671 | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics | Mehul Naik, Samuel Broydo, H. Peter W. Hey | 2003-02-04 |