Issued Patents 2002
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6500357 | System level in-situ integrated dielectric etch process particularly useful for copper dual damascene | Claes Bjorkman, Brian Sy-Yuan Shieh, Gerald Yin | 2002-12-31 |
| 6392290 | Vertical structure for semiconductor wafer-level chip scale packages | Y. Mohammed Kasem, Yueh-Se Ho, Chang-Sheng Chen, Eddy Tjhia, Bosco Lan +2 more | 2002-05-21 |