HT

Hua Tan

YC Yangtze Memory Technologies Co.: 12 patents #75 of 626Top 15%
ES Essenlix: 11 patents #8 of 16Top 50%
UP Utac Headquarters Pte.: 10 patents #3 of 101Top 3%
NA Nanonex: 10 patents #2 of 9Top 25%
Micron: 9 patents #1,566 of 6,345Top 25%
HP HP: 4 patents #3,523 of 16,619Top 25%
PU Princeton University: 2 patents #307 of 1,197Top 30%
ST Sandisk Technologies: 2 patents #967 of 2,224Top 45%
WT Western Digital Technologies: 2 patents #1,273 of 3,180Top 45%
Caltech: 1 patents #2,143 of 4,321Top 50%
Overall (All Time): #26,643 of 4,157,543Top 1%
73
Patents All Time

Issued Patents All Time

Showing 26–50 of 73 patents

Patent #TitleCo-InventorsDate
11719685 Selection method of base asphalt for rubber asphalt based on grey relational analysis Honggang Zhang, Jizong Tan, Haitao Yuan, Hongbo Zhang, Baolin Xiong +3 more 2023-08-08
11710681 Semiconductor packages and methods of packaging semiconductor devices Tanawan Chaowasakoo, Alexander Lucero Laylo, Thanawat Jaengkrajarng 2023-07-25
11687291 Techniques for non-consecutive logical addresses Fangwen Zhou, Wenjing Chen 2023-06-27
11676934 Clip bond semiconductor packages and assembly tools Albert Louis Bove, Aaron Tan 2023-06-13
11670375 Memory with improved cross temperature reliability and read performance Jingxun Eric Wu, Yingying Zhu, Hui-Kap Yang, Bo Zhou 2023-06-06
11648551 Sample manipulation and assay with rapid temperature change Stephen Y. Chou, Wei Ding, Ji Qi, Yufan Zhang 2023-05-16
11379367 Enhancement for activation and deactivation of memory address regions Nicola Colella, Antonino Pollio 2022-07-05
11369968 Molecular manipulation and assay with controlled temperature (II) Stephen Y. Chou, Wei Ding, Yufan Zhang 2022-06-28
11177301 Reliable semiconductor packages Chee Kay Chow, Thian Hwee Tan, Wedanni Linsangan Micla, Enrique Jr Sarile, Mario Arwin Simon Fabian +6 more 2021-11-16
11145575 Conductive bonding layer with spacers between a package substrate and chip Tanawan Chaowasakoo, Alexander Lucero Laylo, Thanawat Jaengkrajarng 2021-10-12
11139233 Cavity wall structure for semiconductor packaging Wilson Poh Leng Ong, Kriangsak Sae Le, Saravuth Sirinorakul, Somsak Phukronghin, Paweena Phatto 2021-10-05
11107533 Memory with improved cross temperature reliability and read performance Jingxun Eric Wu, Yingying Zhu, Hui-Kap Yang, Bo Zhou 2021-08-31
D912842 Assay plate Stephen Y. Chou, Wei Ding, Ji Qi 2021-03-09
10926265 Molecular manipulation and assay with controlled temperature (II) Stephen Y. Chou, Wei Ding, Yufan Zhang 2021-02-23
D910203 Assay plate with sample landing mark Stephen Y. Chou, Wei Ding, Ji Qi 2021-02-09
D910202 Assay plate with sample landing mark Stephen Y. Chou, Wei Ding, Ji Qi 2021-02-09
D898939 Assay plate with sample landing mark Stephen Y. Chou, Wei Ding, Ji Qi 2020-10-13
10792944 Drying media Gary Tarver, Jayanta C. Panditaratne, Jason Hower, James Kearns 2020-10-06
D898224 Assay plate with sample landing mark Stephen Y. Chou, Wei Ding, Ji Qi 2020-10-06
D898222 Assay card Stephen Y. Chou, Wei Ding, Ji Qi 2020-10-06
D898221 Assay plate Stephen Y. Chou, Wei Ding, Ji Qi 2020-10-06
D897555 Assay card Stephen Y. Chou, Wei Ding, Ji Qi 2020-09-29
D893469 Phone holder Stephen Y. Chou, Wei Ding, Ji Qi 2020-08-18
D893470 Phone holder Stephen Y. Chou, Wei Ding, Ji Qi 2020-08-18
10707161 Cavity wall structure for semiconductor packaging Wilson Poh Leng Ong, Kriangsak Sae Le, Saravuth Sirinorakul, Somsak Phukronghin, Paweena Phatto 2020-07-07