Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
AP

Antonino Pollio — 24 Patents

Micron: 24 patents #773 of 6,374Top 15%
Vico Equense, IT: #1 of 5 inventorsTop 20%
Overall (All Time): #168,038 of 4,157,543Top 5%
24 Patents All Time
Antonino Pollio has been granted 24 US patents while listed as an inventor at Micron. The first was granted in 2014 and the most recent in July 2025. Antonino Pollio ranks #168,038 of 4,157,543 US inventors in our database (top 4.0%). Patent records list Antonino Pollio in Vico Equense, IT.

Patents per Year

Patents granted per year, 2014 to 2025Bar chart with a peak of 6 patents in 2024.peak 62014: 2 patents20142015: 2 patents20152017: 1 patents20172018: 2 patents20182020: 1 patents20202021: 1 patents20212022: 4 patents20222023: 3 patents20232024: 6 patents20242025: 2 patents2025

Issued Patents All Time

Showing 1–24 of 24 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12360914 Dynamic updates to logical-to-physical address translation table bitmaps Nicola Colella, Gianfranco Ferrante 2025-07-15
12353750 Idle mode temperature control for memory systems Francesco Basso, Francesco Falanga, Massimo Iaculo 2025-07-08
12183407 Setting switching for single-level cells Umberto Siciliani, Tao Liu, Ting Luo, Dionisio Minopoli, Giuseppe D'Eliseo +6 more 2024-12-31 $26,584,000
12141059 Data separation for garbage collection Nicola Colella 2024-11-12 $38,266,000
12039189 Idle mode temperature control for memory systems Francesco Basso, Francesco Falanga, Massimo Iaculo 2024-07-16 $30,823,000
12007897 Split cache for address mapping data Nicola Colella 2024-06-11 $41,642,000
11928063 Dynamic updates to logical-to-physical address translation table bitmaps Nicola Colella, Gianfranco Ferrante 2024-03-12 $21,460,000
11886341 Enhancement for activation and deactivation of memory address regions Nicola Colella, Hua Tan 2024-01-30 $12,191,000
11768627 Techniques for page line filler data Nicola Colella, Gianfranco Ferrante 2023-09-26 $14,458,000
11657878 Initialization techniques for memory devices Giuseppe Vito Portacci, Mauro Sali, Alessandro Magnavacca 2023-05-23 $14,313,000
11556275 Techniques for page line filler data Nicola Colella, Gianfranco Ferrante 2023-01-17 $11,545,000
11513952 Data separation for garbage collection Nicola Colella 2022-11-29 $10,551,000
11429528 Split cache for address mapping data Nicola Colella 2022-08-30 $13,952,000
11379367 Enhancement for activation and deactivation of memory address regions Nicola Colella, Hua Tan 2022-07-05 $11,496,000
11238940 Initialization techniques for memory devices Giuseppe Vito Portacci, Mauro Sali, Alessandro Magnavacca 2022-02-01 $13,825,000
11023167 Methods and apparatuses for executing a plurality of queued tasks in a memory Giuseppe D'Eliseo, Graziano Mirichigni, Danilo Caraccio, Luca Porzio 2021-06-01 $25,615,000
10614899 Program progress monitoring in a memory array Giuseppe Cariello, Fulvio Rori 2020-04-07 $18,859,000
10108372 Methods and apparatuses for executing a plurality of queued tasks in a memory Giuseppe D'Eliseo, Graziano Mirichigni, Danilo Caraccio, Luca Porzio 2018-10-23 $29,710,000
9971536 Controller to manage NAND memories Federico Tiziani, Giovanni Campardo, Massimo Iaculo, Claudio Giaccio, Manuela Scognamiglio +2 more 2018-05-15 $61,592,000
9569129 Controller to manage NAND memories Federico Tiziani, Giovanni Campardo, Massimo Iaculo, Claudio Giaccio, Manuela Scognamiglio +2 more 2017-02-14 $16,273,000
9213603 Controller to manage NAND memories Federico Tiziani, Giovanni Campardo, Massimo Iaculo, Claudio Giaccio, Manuela Scognamiglio +2 more 2015-12-15 $10,866,000
9189390 Wear leveling for erasable memories Massimo Iaculo, Ornella Vitale 2015-11-17 $12,737,000
8806293 Controller to execute error correcting code algorithms and manage NAND memories Federico Tiziani, Giovanni Campardo, Massimo Iaculo, Claudio Giaccio, Manuela Scognamiglio +2 more 2014-08-12 $7,951,000
8694718 Wear leveling for erasable memories Massimo Iaculo, Ornella Vitale 2014-04-08 $8,842,000