Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12360914 | Dynamic updates to logical-to-physical address translation table bitmaps | Nicola Colella, Gianfranco Ferrante | 2025-07-15 |
| 12353750 | Idle mode temperature control for memory systems | Francesco Basso, Francesco Falanga, Massimo Iaculo | 2025-07-08 |
| 12183407 | Setting switching for single-level cells | Umberto Siciliani, Tao Liu, Ting Luo, Dionisio Minopoli, Giuseppe D'Eliseo +6 more | 2024-12-31 |
| 12141059 | Data separation for garbage collection | Nicola Colella | 2024-11-12 |
| 12039189 | Idle mode temperature control for memory systems | Francesco Basso, Francesco Falanga, Massimo Iaculo | 2024-07-16 |
| 12007897 | Split cache for address mapping data | Nicola Colella | 2024-06-11 |
| 11928063 | Dynamic updates to logical-to-physical address translation table bitmaps | Nicola Colella, Gianfranco Ferrante | 2024-03-12 |
| 11886341 | Enhancement for activation and deactivation of memory address regions | Nicola Colella, Hua Tan | 2024-01-30 |
| 11768627 | Techniques for page line filler data | Nicola Colella, Gianfranco Ferrante | 2023-09-26 |
| 11657878 | Initialization techniques for memory devices | Giuseppe Vito Portacci, Mauro Sali, Alessandro Magnavacca | 2023-05-23 |
| 11556275 | Techniques for page line filler data | Nicola Colella, Gianfranco Ferrante | 2023-01-17 |
| 11513952 | Data separation for garbage collection | Nicola Colella | 2022-11-29 |
| 11429528 | Split cache for address mapping data | Nicola Colella | 2022-08-30 |
| 11379367 | Enhancement for activation and deactivation of memory address regions | Nicola Colella, Hua Tan | 2022-07-05 |
| 11238940 | Initialization techniques for memory devices | Giuseppe Vito Portacci, Mauro Sali, Alessandro Magnavacca | 2022-02-01 |
| 11023167 | Methods and apparatuses for executing a plurality of queued tasks in a memory | Giuseppe D'Eliseo, Graziano Mirichigni, Danilo Caraccio, Luca Porzio | 2021-06-01 |
| 10614899 | Program progress monitoring in a memory array | Giuseppe Cariello, Fulvio Rori | 2020-04-07 |
| 10108372 | Methods and apparatuses for executing a plurality of queued tasks in a memory | Giuseppe D'Eliseo, Graziano Mirichigni, Danilo Caraccio, Luca Porzio | 2018-10-23 |
| 9971536 | Controller to manage NAND memories | Federico Tiziani, Giovanni Campardo, Massimo Iaculo, Claudio Giaccio, Manuela Scognamiglio +2 more | 2018-05-15 |
| 9569129 | Controller to manage NAND memories | Federico Tiziani, Giovanni Campardo, Massimo Iaculo, Claudio Giaccio, Manuela Scognamiglio +2 more | 2017-02-14 |
| 9213603 | Controller to manage NAND memories | Federico Tiziani, Giovanni Campardo, Massimo Iaculo, Claudio Giaccio, Manuela Scognamiglio +2 more | 2015-12-15 |
| 9189390 | Wear leveling for erasable memories | Massimo Iaculo, Ornella Vitale | 2015-11-17 |
| 8806293 | Controller to execute error correcting code algorithms and manage NAND memories | Federico Tiziani, Giovanni Campardo, Massimo Iaculo, Claudio Giaccio, Manuela Scognamiglio +2 more | 2014-08-12 |
| 8694718 | Wear leveling for erasable memories | Massimo Iaculo, Ornella Vitale | 2014-04-08 |