DN

David B. Noddin

WG W.L. Gore & Associates Gmbh: 16 patents #39 of 1,175Top 4%
RO Rogers: 2 patents #58 of 245Top 25%
SP Supercomputer Systems Limited Partnership: 1 patents #27 of 59Top 50%
📍 Ledyard, CT: #8 of 107 inventorsTop 8%
🗺 Connecticut: #1,981 of 34,797 inventorsTop 6%
Overall (All Time): #226,304 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDate
6203891 Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias 2001-03-20
6184589 Constraining ring for use in electronic packaging John J. Budnaitis, Paul J. Fischer, David A. Hanson, Mark F. Sylvester, William George Petefish 2001-02-06
6132853 Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias 2000-10-17
6130015 Method for using fiducial schemes to increase nominal registration during manufacture of laminated circuit Donald G. Hutchins 2000-10-10
6127250 Method of increasing package reliability by designing in plane CTE gradients Mark F. Sylvester 2000-10-03
6103992 Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias 2000-08-15
6023041 Method for using photoabsorptive coatings and consumable copper to control exit via redeposit as well as diameter variance 2000-02-08
6018196 Semiconductor flip chip package 2000-01-25
6011697 Constraining ring for use in electronic packaging John J. Budnaitis, Paul J. Fischer, David A. Hanson, Mark F. Sylvester, William George Petefish 2000-01-04
5973290 Laser apparatus having improved via processing rate 1999-10-26
5965043 Method for using ultrasonic treatment in combination with UV-lasers to enable plating of high aspect ratio micro-vias Robin E. Gorrell, Michael R. Leaf 1999-10-12
5910255 Method of sequential laser processing to efficiently manufacture modules requiring large volumetric density material removal for micro-via formation 1999-06-08
5888630 Apparatus and method for unit area composition control to minimize warp in an integrated circuit chip package assembly Mark F. Sylvester 1999-03-30
5879786 Constraining ring for use in electronic packaging John J. Budnaitis, Paul J. Fischer, David A. Hanson, Mark F. Sylvester, William George Petefish 1999-03-09
5868950 Method to correct astigmatism of fourth yag to enable formation of sub 25 micron micro-vias using masking techniques 1999-02-09
5841102 Multiple pulse space processing to enhance via entrance formation at 355 nm 1998-11-24
5731047 Multiple frequency processing to improve electrical resistivity of blind micro-vias 1998-03-24
5276955 Multilayer interconnect system for an area array interconnection using solid state diffusion Robin E. Gorrell, William George Petefish, Kevin L. Stumpe, Boydd Piper, Deepak Swamy +2 more 1994-01-11
5046238 Method of manufacturing a multilayer circuit board Robert C. Daigle, Samuel Malbaurn 1991-09-10
4915981 Method of laser drilling fluoropolymer materials Richard T. Traskos, Cathy Fleischer, Carlos L. Barton 1990-04-10