Issued Patents All Time
Showing 26–50 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10088881 | Mechanism to preclude I/O-dependent load replays in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-10-02 |
| 10083038 | Mechanism to preclude load replays dependent on page walks in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-09-25 |
| 10019260 | Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match | G. Glenn Henry, Rodney E. Hooker, Terry Parks | 2018-07-10 |
| 9952875 | Microprocessor with ALU integrated into store unit | Gerard M. Col, Rodney E. Hooker | 2018-04-24 |
| 9915998 | Power saving mechanism to reduce load replays in out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-03-13 |
| 9910785 | Cache memory budgeted by ways based on memory access type | Rodney E. Hooker, Douglas R. Reed, John Michael Greer | 2018-03-06 |
| 9898418 | Processor including single invalidate page instruction | — | 2018-02-20 |
| 9898411 | Cache memory budgeted by chunks based on memory access type | Rodney E. Hooker, Douglas R. Reed, John Michael Greer | 2018-02-20 |
| 9842055 | Address translation cache that supports simultaneous invalidation of common context entries | Viswanath Mohan | 2017-12-12 |
| 9817764 | Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type | Rodney E. Hooker, Douglas R. Reed, John Michael Greer | 2017-11-14 |
| 9811468 | Set associative cache memory with heterogeneous replacement policy | Rodney E. Hooker, Douglas R. Reed, John Michael Greer | 2017-11-07 |
| 9804845 | Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2017-10-31 |
| 9798675 | System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructions | Brent Bean | 2017-10-24 |
| 9798669 | System and method of determining memory ownership on cache line basis for detecting self-modifying code | Brent Bean | 2017-10-24 |
| 9798670 | System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction | Brent Bean | 2017-10-24 |
| 9792216 | System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries | Brent Bean | 2017-10-17 |
| 9792223 | Processor including load EPT instruction | Terry Parks | 2017-10-17 |
| 9760496 | Simultaneous invalidation of all address translation cache entries associated with an X86 process context identifier | — | 2017-09-12 |
| 9740271 | Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2017-08-22 |
| 9727480 | Efficient address translation caching in a processor that supports a large number of different address spaces | Terry Parks, Viswanath Mohan, John Bunda | 2017-08-08 |
| 9703359 | Power saving mechanism to reduce load replays in out-of-order processor | Gerard M. Col, G. Glenn Henry | 2017-07-11 |
| 9652400 | Fully associative cache memory budgeted by memory access type | Rodney E. Hooker, Douglas R. Reed, John Michael Greer, Albert J. Loper | 2017-05-16 |
| 9652398 | Cache replacement policy that considers memory access type | Rodney E. Hooker, Douglas R. Reed, John Michael Greer, Terry Parks | 2017-05-16 |
| 9645827 | Mechanism to preclude load replays dependent on page walks in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2017-05-09 |
| 9645822 | Conditional store instructions in an out-of-order execution microprocessor | G. Glenn Henry, Terry Parks, Rodney E. Hooker, Gerard M. Col | 2017-05-09 |