Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9569363 | Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry | Rodney E. Hooker | 2017-02-14 |
| 9542332 | System and method for performing hardware prefetch tablewalks having lowest tablewalk priority | — | 2017-01-10 |
| 9501286 | Microprocessor with ALU integrated into load unit | Gerard M. Col, Rodney E. Hooker | 2016-11-22 |
| 9378019 | Conditional load instructions in an out-of-order execution microprocessor | G. Glenn Henry, Terry Parks, Rodney E. Hooker, Gerard M. Col | 2016-06-28 |
| 9244686 | Microprocessor that translates conditional load/store instructions into variable number of microinstructions | G. Glenn Henry, Terry Parks, Rodney E. Hooker, Gerard M. Col | 2016-01-26 |
| 8782348 | Microprocessor cache line evict array | Rodney E. Hooker | 2014-07-15 |
| 8566565 | Microprocessor with multiple operating modes dynamically configurable by a device driver based on currently running applications | Rodney E. Hooker, G. Glenn Henry | 2013-10-22 |
| 8543765 | Efficient data prefetching in the presence of load hits | Clinton Thomas Glover, Rodney E. Hooker, Albert J. Loper | 2013-09-24 |
| 8539209 | Microprocessor that performs a two-pass breakpoint check for a cache line-crossing load/store operation | Bryan Wayne Pogor | 2013-09-17 |
| 8533437 | Guaranteed prefetch instruction | G. Glenn Henry, Rodney E. Hooker | 2013-09-10 |
| 8533438 | Store-to-load forwarding based on load/store address computation source information comparisons | Rodney E. Hooker | 2013-09-10 |
| 8489823 | Efficient data prefetching in the presence of load hits | Clinton Thomas Glover, Rodney E. Hooker, Albert J. Loper | 2013-07-16 |
| 8433853 | Prefetching of next physically sequential cache line after cache line that includes loaded page table entry | Rodney E. Hooker | 2013-04-30 |
| 8392666 | Low power high speed load-store collision detector | Rodney E. Hooker | 2013-03-05 |
| 8392693 | Fast REP STOS using grabline operations | G. Glenn Henry, Rodney E. Hooker | 2013-03-05 |
| 8364906 | Avoiding memory access latency by returning hit-modified when holding non-modified data | Rodney E. Hooker, Darius D. Gaskins, Albert J. Loper | 2013-01-29 |
| 8301842 | Efficient pseudo-LRU for colliding accesses | Rodney E. Hooker | 2012-10-30 |
| 8291172 | Multi-modal data prefetcher | Rodney E. Hooker | 2012-10-16 |
| 8234450 | Efficient data prefetching in the presence of load hits | Clinton Thomas Glover, Rodney E. Hooker, Albert J. Loper | 2012-07-31 |
| 8161246 | Prefetching of next physically sequential cache line after cache line that includes loaded page table entry | Rodney E. Hooker | 2012-04-17 |
| 8108624 | Data cache with modified bit array | Rodney E. Hooker, G. Glenn Henry | 2012-01-31 |
| 8108621 | Data cache with modified bit array | Rodney E. Hooker, G. Glenn Henry | 2012-01-31 |
| 8069340 | Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions | Rodney E. Hooker, Gerard M. Col | 2011-11-29 |
| 7996650 | Microprocessor that performs speculative tablewalks | Rodney E. Hooker | 2011-08-09 |
| 7827390 | Microprocessor with private microcode RAM | G. Glenn Henry, Rodney E. Hooker, Terry Parks | 2010-11-02 |