Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9190359 | Scribe line structure for wafer dicing and method of making the same | Tsung-Shu Lin | 2015-11-17 |
| 8610252 | Scribe line structure for wafer dicing | Tsung-Shu Lin | 2013-12-17 |
| 8115320 | Bond pad structure located over active circuit structure | — | 2012-02-14 |
| 8039367 | Scribe line structure and method for dicing a wafer | — | 2011-10-18 |
| 8030778 | Integrated circuit structure and manufacturing method thereof | — | 2011-10-04 |
| 8013425 | Scribe line structure for wafer dicing and method of making the same | Tsung-Shu Lin | 2011-09-06 |
| 7795704 | Die seal ring and wafer having the same | — | 2010-09-14 |
| 7696606 | Metal structure | Chien-Li Kuo, Jui-Meng Jao, Hui-Ling Chen, Kai-Kuang Ho, Ching-Li Yang | 2010-04-13 |
| 7649268 | Semiconductor wafer | Chien-Li Kuo, Jui-Meng Jao, Hui-Ling Chen, Kai-Kuang Ho, Ching-Li Yang | 2010-01-19 |
| 7485953 | Chip package structure | — | 2009-02-03 |
| 7387950 | Method for forming a metal structure | Chien-Li Kuo, Jui-Meng Jao, Hui-Ling Chen, Kai-Kuang Ho, Ching-Li Yang | 2008-06-17 |
| 7382038 | Semiconductor wafer and method for making the same | — | 2008-06-03 |
| 7129574 | Multi-power ring chip scale package for system level integration | — | 2006-10-31 |
| 6770963 | Multi-power ring chip scale package for system level integration | — | 2004-08-03 |
| 6586292 | Guard mesh for noise isolation in highly integrated circuits | Chinpo Chen | 2003-07-01 |
| 6424022 | Guard mesh for noise isolation in highly integrated circuits | Chinpo Chen | 2002-07-23 |