Issued Patents All Time
Showing 76–95 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7162661 | Systematic and random error detection and recovery within processing stages of an integrated circuit | Trevor Nigel Mudge, Todd Michael Austin, Krisztian Flautner | 2007-01-09 |
| 7149674 | Methods for analyzing integrated circuits and apparatus therefor | Supamas Sirichotiyakul, Timothy J. Edwards, Chanhee OH, Rajendran Panda, Judah L. Adelman +2 more | 2006-12-12 |
| 7093223 | Noise analysis for an integrated circuit model | Murat Becer, Ilan Algor, Rajendran Panda | 2006-08-15 |
| 7072229 | Memory system having fast and slow data reading mechanisms | Todd Michael Austin, Trevor Nigel Mudge, Dennis Sylvester, Krisztian Flautner | 2006-07-04 |
| 7055007 | Data processor memory circuit | Krisztian Flautner, Trevor Nigel Mudge, Nam Sung Kim, Steven M. Martin | 2006-05-30 |
| 6944067 | Memory system having fast and slow data reading mechanisms | Trevor Nigel Mudge, Todd Michael Austin, Dennis Sylvester, Krisztian Flautner | 2005-09-13 |
| 6919619 | Actively-shielded signal wires | Dennis Sylvester, Himanshu Kaul | 2005-07-19 |
| 6819538 | Method and apparatus for controlling current demand in an integrated circuit | Rajendran Panda, Rajat Chaudhry, Vladimir Zolotov, Ravindraraj Ramaraju | 2004-11-16 |
| 6799153 | Cross coupling delay characterization for integrated circuits | Supamas Sirichotiyakul, Chanhee OH, Vladimir Zolotov, Rafi Levy | 2004-09-28 |
| 6480998 | Iterative, noise-sensitive method of routing semiconductor nets using a delay noise threshold | Pradipto Mukherjee, Aurobindo Dasgupta, David R. Bearden | 2002-11-12 |
| 6074429 | Optimizing combinational circuit layout through iterative restructuring | Satyamurthy Pullela, Stephen C. Moore, Rajendran Panda, Gopalakrishnan Vijayan | 2000-06-13 |
| 5903471 | Method for optimizing element sizes in a semiconductor device | Satyamurthy Pullela, Timothy J. Edwards, Joseph W. Norton, Abhijit Dharchoudhury | 1999-05-11 |
| 5790415 | Complementary network reduction for load modeling | Satyamurthy Pullela, Abhijit Dharchoudhury, Tim J. Edwards, Joseph W. Norton | 1998-08-04 |
| 5790416 | Updating hierarchical DAG representations through a bottom up method | Joseph W. Norton, Larry G. Jones | 1998-08-04 |
| 5787008 | Simulation corrected sensitivity | Satyamurthy Pullela, Abhijit Dharchoudhury, Tim J. Edwards, Joseph W. Norton, Peter R. O'Brien | 1998-07-28 |
| 5751593 | Accurate delay prediction based on multi-model analysis | Satyamurthy Pullela, Abhijit Dharchoudhury, Tim J. Edwards, Joseph W. Norton | 1998-05-12 |
| 5737236 | Apparatus and method for the automatic determination of a standard library height within an integrated circuit design | Robert L. Maziasz, Mohankumar Guruswamy, Daniel Dulitz, Larry G. Jones | 1998-04-07 |
| 5689432 | Integrated circuit design and manufacturing method and an apparatus for designing an integrated circuit in accordance with the method | Robert L. Maziasz, Joseph W. Norton, Larry G. Jones, Mohankumar Guruswamy | 1997-11-18 |
| 5666288 | Method and apparatus for designing an integrated circuit | Larry G. Jones, Robert L. Maziasz, Mohan Guruswamy | 1997-09-09 |
| 5619418 | Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized | Joseph W. Norton, Larry G. Jones, Susanta Misra, R. Iris Bahar | 1997-04-08 |