Issued Patents All Time
Showing 51–75 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8407537 | Error recover within processing stages of an integrated circuit | Krisztian Flautner, Todd Michael Austin, Trevor Nigel Mudge | 2013-03-26 |
| 8407025 | Operating parameter control of an apparatus for processing data | Dennis Sylvester, David Fick, Stuart David Biles, Michael J. Wieckowski, Scott Hanson +1 more | 2013-03-26 |
| 8346832 | Random number generator | Trevor Nigel Mudge, Carlos Tokunaga | 2013-01-01 |
| 8335122 | Cache memory system for a data processing apparatus | Ronald George Dreslinski, Gregory K. Chen, Trevor Nigel Mudge, Dennis Sylvester | 2012-12-18 |
| 8276014 | Stalling synchronisation circuits in response to a late data signal | Matthew Rudolph Fojtik, Dennis Sylvester, David Fick | 2012-09-25 |
| 8255610 | Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry | Sudhir K. Satpathy, Trevor Nigel Mudge, Dennis Sylvester | 2012-08-28 |
| 8230152 | Crossbar circuitry and method of operation of such crossbar circuitry | Sudhir K. Satpathy, Trevor Nigel Mudge, Dennis Sylvester | 2012-07-24 |
| 8185812 | Single event upset error detection within an integrated circuit | Shidhartha Das, David Michael Bull | 2012-05-22 |
| 8185786 | Error recovery within processing stages of an integrated circuit | Krisztian Flautner, Todd Michael Austin, Trevor Nigel Mudge | 2012-05-22 |
| 8108585 | Crossbar circuitry and method of operation of such crossbar circuitry | Sudhir K. Satpathy, Trevor Nigel Mudge, Dennis Sylvester, Ronald George Dreslinski | 2012-01-31 |
| 8107290 | Memory cell structure, a memory device employing such a memory cell structure, and an integrated circuit having such a memory device | Yoonmyung Lee, Michael J. Wieckowski, Dennis Sylvester | 2012-01-31 |
| 8103922 | Error detection in precharged logic | David Michael Bull, Shidhartha Das | 2012-01-24 |
| 8060814 | Error recovery within processing stages of an integrated circuit | Shidhartha Das, Todd Michael Austin | 2011-11-15 |
| 8006147 | Error detection in precharged logic | David Michael Bull, Shidhartha Das | 2011-08-23 |
| 7880339 | Isolation circuitry and method for hiding a power consumption characteristic of an associated processing circuit | Carlos Tokunaga | 2011-02-01 |
| 7864562 | Integrated circuit memory access mechanisms | Gregory K. Chen, Dennis Sylvester | 2011-01-04 |
| 7839129 | On-chip power supply voltage regulation | Sanjay Pant | 2010-11-23 |
| 7701240 | Integrated circuit with error correction mechanisms to offset narrow tolerancing | Krisztian Flautner, David Michael Bull, Todd Michael Austin, Trevor Nigel Mudge | 2010-04-20 |
| 7650551 | Error detection and recovery within processing stages of an integrated circuit | Krisztian Flautner, Todd Michael Austin, Trevor Nigel Mudge | 2010-01-19 |
| 7533226 | Data processor memory circuit | Krisztian Flautner, Trevor Nigel Mudge, Nam Sung Kim, Steven M. Martin | 2009-05-12 |
| 7337356 | Systematic and random error detection and recovery within processing stages of an integrated circuit | Trevor Nigel Mudge, Todd Michael Austin, Krisztian Flautner | 2008-02-26 |
| 7320091 | Error recovery within processing stages of an integrated circuit | David Michael Bull, Shidhartha Das | 2008-01-15 |
| 7310755 | Data retention latch provision within integrated circuits | Trevor Nigel Mudge, Todd Michael Austin, Krisztian Flautner | 2007-12-18 |
| 7278080 | Error detection and recovery within processing stages of an integrated circuit | Krisztian Flautner, Todd Michael Austin, Trevor Nigel Mudge | 2007-10-02 |
| 7263015 | Address decoding | David Michael Bull, Shidhartha Das | 2007-08-28 |