Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5751162 | Field programmable gate array logic module configurable as combinational or sequential circuits | Mahesh M. Mehendale, Manisha Agarwala, Mark G. Harward, Robert J. Landers | 1998-05-12 |
| 5751987 | Distributed processing memory chip with embedded logic having both data memory and broadcast memory | Derek Smith, Basavaraj I. Pawate, George R. Doddington, Warren L. Bean, Mark G. Harward +1 more | 1998-05-12 |
| 5723988 | CMOS with parasitic bipolar transistor | Mark G. Harward, Lawrence A. Arledge, Jr., Ravishankar Sundaresan | 1998-03-03 |
| 5699287 | Method and device for adding and subtracting thermometer coded data | Fuk Ho Pius Ng | 1997-12-16 |
| 5654981 | Signal transmission system and method of operation | Robert J. Landers | 1997-08-05 |
| 5652441 | Gate array base cell with novel gate structure | Mashashi Hashimoto | 1997-07-29 |
| 5646877 | High radix multiplier architecture | Carl E. Lemonds | 1997-07-08 |
| 5612632 | High speed flip-flop for gate array | Kevin M. Ovens, Clive Bittlestone, Robert C. Martin, Robert J. Landers | 1997-03-18 |
| 5563430 | Gate array base cell | Masashi Hashimoto | 1996-10-08 |
| 5535241 | Signal transmission system and method of operation | Robert J. Landers | 1996-07-09 |
| 5528549 | Apparatus, systems and methods for distributed signal processing | George R. Doddington, Basavaraj I. Pawate, Derek Smith | 1996-06-18 |
| 5528550 | Apparatus, systems and methods for implementing memory embedded search arithmetic logic unit | Basavaraj I. Pawate, George R. Doddington, Derek Smith | 1996-06-18 |
| 5502404 | Gate array cell with predefined connection patterns | Robert J. Landers, R. Krishman, C. Mutukrishnan | 1996-03-26 |
| 5500828 | Apparatus, system and methods for distributed signal processing | George D. Doddington, Basavaraj I. Pawate, Derek Smith | 1996-03-19 |
| 5488315 | Adder-based base cell for field programmable gate arrays | Manisha Agarwala, Mahesh M. Mehendale, Robert J. Landers, Mark G. Harward | 1996-01-30 |
| 5479034 | Method of making gate array base cell | Mashashi Hashimoto | 1995-12-26 |
| 5469079 | Flip-flop for use in LSSD gate arrays | Robert J. Landers | 1995-11-21 |
| 5422581 | Gate array cell with predefined connection patterns | Robert J. Landers | 1995-06-06 |
| 5398198 | Single integrated circuit having both a memory array and an arithmetic and logic unit (ALU) | Shobana Swamy | 1995-03-14 |
| 5391943 | Gate array cell with predefined connection patterns | Robert J. Landers | 1995-02-21 |
| 5390139 | Devices, systems and methods for implementing a Kanerva memory | Derek Smith, Basavaraj I. Pawate, George R. Doddington, Warren L. Bean | 1995-02-14 |
| 5369046 | Method for forming a gate array base cell | Masahashi Hashimoto | 1994-11-29 |
| 5367702 | System and method for approximating nonlinear functions | Thomas J. Aton, Jerold A. Seitchik | 1994-11-22 |
| 5352924 | Bipolar layout for improved performance | David B. Scott | 1994-10-04 |
| 5345196 | Method and apparatus for current and voltage control of an oscillator | John W. Fattaruso | 1994-09-06 |