Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8352035 | Connector assemblies for implantable stimulators | Brett Schleicher, Rafael Carbunaru, Todd K. Whitehurst, Kristen N. Jaax, Andrew DiGiore | 2013-01-08 |
| 8344479 | Integrated circuit inductor with integrated vias | Robert L. Pitts | 2013-01-01 |
| 8260434 | Paddle lead configurations for electrical stimulation systems and methods of making and using | Andrew DiGiore | 2012-09-04 |
| 8260432 | Moldable charger with shape-sensing means for an implantable pulse generator | Andrew DiGiore, Brett Schleicher | 2012-09-04 |
| 8232158 | Compensated isolated p-well DENMOS devices | Kamel Benaissa, Vineet Mishra, Ananth Kamath | 2012-07-31 |
| 8114729 | Differential poly doping and circuits therefrom | Shashank S. Ekbote, Kamel Benaissa, Borna J. Obradovic | 2012-02-14 |
| 7994009 | Low cost transistors using gate orientation and optimized implants | Kamel Benaissa, Shaofeng Yu, Shashank S. Ekbote | 2011-08-09 |
| 7888227 | Integrated circuit inductor with integrated vias | Robert L. Pitts | 2011-02-15 |
| 7718482 | CD gate bias reduction and differential N+ poly doping for CMOS circuits | Shashank S. Ekbote, Borna J. Obradovic | 2010-05-18 |
| 7400025 | Integrated circuit inductor with integrated vias | Robert L. Pitts | 2008-07-15 |
| 7202537 | Versatile system for limiting electric field degradation of semiconductor structures | Periannan Chidambaram | 2007-04-10 |
| 7101751 | Versatile system for limiting electric field degradation of semiconductor structures | PR Chidambaram | 2006-09-05 |
| 6730554 | Multi-layer silicide block process | Freidoon Mehrad | 2004-05-04 |
| 6727133 | Integrated circuit resistors in a high performance CMOS process | — | 2004-04-27 |
| 6333238 | Method for minimizing the temperature coefficient of resistance of passive resistors in an integrated circuit process flow | Alwin Tsao | 2001-12-25 |
| 6211769 | System to minimize the temperature coefficient of resistance of passive resistors in an integrated circuit process flow | Alwin Tsao | 2001-04-03 |
| 6150669 | Combination test structures for in-situ measurements during fabrication of semiconductor devices | Mahalingam Nandakumar, Andrew T. Appel | 2000-11-21 |