Issued Patents All Time
Showing 51–54 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8448102 | Optimizing layout of irregular structures in regular layout context | Stephen Kornachuk, James Mali, Brian Reed, Scott T. Becker | 2013-05-21 |
| 8405162 | Integrated circuit including gate electrode level region including cross-coupled transistors having at least one gate contact located over outer portion of gate electrode level region | Scott T. Becker, Jim Mali | 2013-03-26 |
| 8405163 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature | Scott T. Becker, Jim Mali | 2013-03-26 |
| 8395224 | Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes | Scott T. Becker, Jim Mali | 2013-03-12 |