Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8816402 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor | Scott T. Becker, Jim Mali | 2014-08-26 |
| 8785978 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer | Scott T. Becker, Jim Mali | 2014-07-22 |
| 8785979 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer | Scott T. Becker, Jim Mali | 2014-07-22 |
| 8772839 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer | Scott T. Becker, Jim Mali | 2014-07-08 |
| 8742463 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts | Scott T. Becker, Jim Mali | 2014-06-03 |
| 8742462 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications | Scott T. Becker, Jim Mali | 2014-06-03 |
| 8735995 | Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track | Scott T. Becker, Jim Mali | 2014-05-27 |
| 8735944 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors | Scott T. Becker, Jim Mali | 2014-05-27 |
| 8729643 | Cross-coupled transistor circuit including offset inner gate contacts | Scott T. Becker, Jim Mali | 2014-05-20 |
| 8729606 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels | Scott T. Becker, Jim Mali | 2014-05-20 |
| 8701071 | Enforcement of semiconductor structure regularity for localized transistors and interconnect | Stephen Kornachuk, Jim Mali, Scott T. Becker | 2014-04-15 |
| 8680583 | Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels | Scott T. Becker, Jim Mali | 2014-03-25 |
| 8669595 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications | Scott T. Becker, Jim Mali | 2014-03-11 |
| 8669594 | Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels | Scott T. Becker, Jim Mali | 2014-03-11 |
| 8592872 | Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature | Scott T. Becker, Jim Mali | 2013-11-26 |
| 8587034 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer | Scott T. Becker, Jim Mali | 2013-11-19 |
| 8581304 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships | Scott T. Becker, Jim Mali | 2013-11-12 |
| 8581303 | Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer | Scott T. Becker, Jim Mali | 2013-11-12 |
| 8575706 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode | Scott T. Becker, Jim Mali | 2013-11-05 |
| 8569841 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel | Scott T. Becker, Jim Mali | 2013-10-29 |
| 8564071 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact | Scott T. Becker, Jim Mali | 2013-10-22 |
| 8558322 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature | Scott T. Becker, Jim Mali | 2013-10-15 |
| 8552508 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer | Scott T. Becker, Jim Mali | 2013-10-08 |
| 8552509 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors | Scott T. Becker, Jim Mali | 2013-10-08 |
| 8453094 | Enforcement of semiconductor structure regularity for localized transistors and interconnect | Stephen Kornachuk, Jim Mali, Scott T. Becker | 2013-05-28 |