Issued Patents All Time
Showing 101–118 of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6884674 | Method for fabricating a semiconductor device including a capacitance insulating film having a perovskite structure | Akihiko Tsuzumitani, Hisashi Ogawa, Yoshihiro Mori | 2005-04-26 |
| 6773979 | Method for fabricating semiconductor device | Akihiko Tsuzumitani, Yoshihiro Mori | 2004-08-10 |
| 6645807 | Method for manufacturing semiconductor device | Akihiko Tsuzumitani, Toshihiko Nagai | 2003-11-11 |
| 6531729 | Semiconductor device and method for fabricating the same | Akihiko Tsuzumitani, Yoshihiro Mori | 2003-03-11 |
| 6501113 | Semiconductor device with capacitor using high dielectric constant film or ferroelectric film | Yoshikazu Tsunemine | 2002-12-31 |
| 6486520 | Structure and method for a large-permittivity gate using a germanium layer | Scott R. Summerfelt | 2002-11-26 |
| 6436786 | Method for fabricating a semiconductor device | Akihiko Tsuzumitani, Yoshihiro Mori | 2002-08-20 |
| 6342420 | Hexagonally symmetric integrated circuit cell | Akitoshi Nishimura, Rajesh Khamankar, Shane R. Palmer | 2002-01-29 |
| 6335238 | Integrated dielectric and method | Sunil V. Hanttangady, Robert M. Wallace, Bruce E. Gnade | 2002-01-01 |
| 6287903 | Structure and method for a large-permittivity dielectric using a germanium layer | Scott R. Summerfelt | 2001-09-11 |
| 6265262 | Semiconductor device and method of fabricating the same | Akihiko Tsuzumitani, Yoshihiro Mori | 2001-07-24 |
| 6251749 | Shallow trench isolation formation with sidewall spacer | Shigeru Kuroda, Ken Numata | 2001-06-26 |
| 6166408 | Hexagonally symmetric integrated circuit cell | Akitoshi Nishimura, Rajesh Khamankar, Shane R. Palmer | 2000-12-26 |
| 6110842 | Method of forming multiple gate oxide thicknesses using high density plasma nitridation | Sunil Hattangady | 2000-08-29 |
| 6033953 | Method for manufacturing dielectric capacitor, dielectric memory device | Katsuhiro Aoki, Yukio Fukuda, Ken Numata, Akitoshi Nishimura | 2000-03-07 |
| 5814888 | Semiconductor device having a multilayer wiring and the method for fabricating the device | Yasushiro Nishioka, Tsuyoshi Tanaka, Kyung-Ho Park | 1998-09-29 |
| 5616515 | Silicon oxide germanium resonant tunneling | — | 1997-04-01 |
| 5466949 | Silicon oxide germanium resonant tunneling | — | 1995-11-14 |