Issued Patents All Time
Showing 276–300 of 303 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7259050 | Semiconductor device and method of making the same | Chien-Hao Chen, Chia-Lin Chen, Shih-Chang Chen, Ju-Wang Hsu | 2007-08-21 |
| 7235864 | Integrated circuit devices, edge seals therefor | — | 2007-06-26 |
| 7232730 | Method of forming a locally strained transistor | Chien-Hao Chen, Donald Y. Chao | 2007-06-19 |
| 7186662 | Method for forming a hard mask for gate electrode patterning and corresponding device | Chien-Hao Chen, Chia-Jen Chen, Chao-Cheng Chen, Shih-Chang Chen | 2007-03-06 |
| 7176138 | Selective nitride liner formation for shallow trench isolation | Chien-Hao Chen, Vincent S. Chang, Ji-Yi Yang, Chia-Lin Chen | 2007-02-13 |
| 7166525 | High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer | Vincent S. Chang, Chia-Lin Chen, Chi-Chun Chen, Shih-Chang Chen, Chien-Hao Chen | 2007-01-23 |
| 7164163 | Strained transistor with hybrid-strain inducing layer | Chien-Hao Chen | 2007-01-16 |
| 7157350 | Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration | Ji-Yi Yang, Chien-Hao Chen, Shih-Chang Chen, Huan-Just Lin | 2007-01-02 |
| 7129184 | Method of depositing an epitaxial layer of SiGe subsequent to a plasma etch | Chih-Chien Chang, Shun Wu Lin, Pang-Yen Tsai, Shih-Chang Chen | 2006-10-31 |
| 7052946 | Method for selectively stressing MOSFETs to improve charge carrier mobility | Chien-Hao Chen, Chia-Lin Chen, Ju-Wang Hsu, Shih-Chang Chen | 2006-05-30 |
| 7023090 | Bonding pad and via structure design | Tai-Chun Huang | 2006-04-04 |
| 6955981 | Pad structure to prompt excellent bondability for low-k intermetal dielectric layers | Yun-San Huan | 2005-10-18 |
| 6933157 | Semiconductor wafer manufacturing methods employing cleaning delay period | Chia-Lin Chen, Shih-Chang Chen | 2005-08-23 |
| 6911386 | Integrated process for fuse opening and passivation process for CU/LOW-K IMD | Chao-Chen Chen | 2005-06-28 |
| 6876062 | Seal ring and die corner stress relief pattern design to protect against moisture and metallic impurities | Shih Chung Chen, Ming-Soah Liang, Chen-Hua Yu | 2005-04-05 |
| 6864109 | Method and system for determining a component concentration of an integrated circuit feature | Vincent S. Chang, Chi-Chun Chen, Chun-Lin Wu, Shih-Chang Chen | 2005-03-08 |
| 6858944 | Bonding pad metal layer geometry design | Tai-Chun Huang | 2005-02-22 |
| 6830996 | Device performance improvement by heavily doped pre-gate and post polysilicon gate clean | Chia-Lin Chen, Shih-Chang Chen | 2004-12-14 |
| 6825541 | Bump pad design for flip chip bumping | Tai-Chun Huang | 2004-11-30 |
| 6737362 | Method for manufacturing a thin gate dielectric layer for integrated circuit fabrication | Chia-Lin Chen, Chun-Lin Wu, Chi-Chun Chen, Shih-Chang Chen | 2004-05-18 |
| 6727134 | Method of forming a nitride gate dielectric layer for advanced CMOS devices | Chi-Chun Chen, Shih-Chang Chen | 2004-04-27 |
| 6649538 | Method for plasma treating and plasma nitriding gate oxides | Juing-Yi Cheng | 2003-11-18 |
| 6642117 | Method for forming composite dielectric layer | Chi-Chun Chen, Shih-Chang Chen | 2003-11-04 |
| 6551856 | Method for forming copper pad redistribution and device formed | — | 2003-04-22 |
| 6440833 | Method of protecting a copper pad structure during a fuse opening procedure | Mong-Song Liang | 2002-08-27 |