Issued Patents All Time
Showing 126–150 of 161 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157902 | Semiconductor devices with cells comprising routing resources | Mao-Wei Chiu, Hui-Zhong Zhuang, Li-Chun Tien, Chi-Yu Lu | 2018-12-18 |
| 10141256 | Semiconductor device and layout design thereof | Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue | 2018-11-27 |
| 10127340 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Mao-Wei Chiu, Hui-Zhong Zhuang, Li-Chun Tien, Chi-Yu Lu | 2018-11-13 |
| 10007750 | Gate pad layout patterns for masks and structures | Shun Li Chen, Yi-Hsun Chiu, Li-Chun Tien | 2018-06-26 |
| 9991158 | Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Li-Chun Tien +1 more | 2018-06-05 |
| 9899263 | Method of forming layout design | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang +1 more | 2018-02-20 |
| 9882002 | FinFET with an asymmetric source/drain structure and method of making same | Hsiang-Jen Tseng, Wei-Yu Chen, Kuo-Nan Yang, Ming-Hsiang Song, Ta-Pen Guo | 2018-01-30 |
| 9853008 | Connecting techniques for stacked CMOS devices | Hsiang-Jen Tseng, Wei-Yu Chen, Li-Chun Tien | 2017-12-26 |
| 9846759 | Global connection routing method and system for performing the same | Sheng-Hsiung Chen, Jyun-Hao Chang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang | 2017-12-19 |
| 9846757 | Cell grid architecture for FinFET technology | Hui-Zhong Zhuang, Chung-Te Lin, Li-Chun Tien | 2017-12-19 |
| 9831230 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Li-Chun Tien, Ya-Chi Chou, Hui-Zhong Zhuang, Chun-Fu Chen, Hsiang-Jen Tseng | 2017-11-28 |
| 9806071 | Integrated circuit with elongated coupling | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Li-Chun Tien | 2017-10-31 |
| 9767243 | System and method of layout design for integrated circuits | Hui-Zhong Zhuang, Li-Chun Tien | 2017-09-19 |
| 9690892 | Masks based on gate pad layout patterns of standard cell having different gate pad pitches | Shun Li Chen, Yi-Hsun Chiu, Li-Chun Tien | 2017-06-27 |
| 9691750 | Semiconductor device and layout method thereof | Ting Wei Chou, WEN-LANG WU, Chitong Chen, Shun Li Chen, Li-Chun Tien | 2017-06-27 |
| 9659129 | Standard cell having cell height being non-integral multiple of nominal minimum pitch | Shang-Chih Hsieh, Hui-Zhong Zhuang, Chun-Fu Chen, Hsiang-Jen Tseng | 2017-05-23 |
| 9653393 | Method and layout of an integrated circuit | Wei-Yu Chen, Li-Chun Tien, Hui-Zhong Zhuang, Hsiang-Jen Tseng | 2017-05-16 |
| 9641161 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2017-05-02 |
| 9626472 | Method and system of forming layout design | Li-Chun Tien, Hui-Zhong Zhuang, Zhe-Wei Jiang | 2017-04-18 |
| 9536032 | Method and system of layout placement based on multilayer gridlines | Li-Chun Tien, Hui-Zhong Zhuang, Zhe-Wei Jiang | 2017-01-03 |
| 9501600 | Standard cells for predetermined function having different types of layout | Shang-Chih Hsieh, Hui-Zhong Zhuang, Chun-Fu Chen, Hsiang-Jen Tseng | 2016-11-22 |
| 9478609 | Integrated circuit with multiple cells having different heights | Li-Chun Tien, Ming Jin Huang, Pin-Dai Sue | 2016-10-25 |
| 9443758 | Connecting techniques for stacked CMOS devices | Hsiang-Jen Tseng, Wei-Yu Chen, Li-Chun Tien | 2016-09-13 |
| 9431381 | System and method of processing cutting layout and example switching circuit | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Li-Chun Tien | 2016-08-30 |
| 9425141 | Integrated circuit with elongated coupling | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Li-Chun Tien | 2016-08-23 |