Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7251186 | Multi-port memory utilizing an array of single-port memory cells | Deepak Sabharwal, Prakash Bhatia, Shreekanth Sampigethaya, Sanjiv Kainth | 2007-07-31 |
| 7200793 | Error checking and correcting for content addressable memories (CAMs) | David W. Carr, Paul Nadj, Jaya Prakash Samala | 2007-04-03 |
| 6459647 | Split-bank architecture for high performance SDRAMs | — | 2002-10-01 |
| 6452834 | 2T dual-port DRAM in a pure logic process with non-destructive read capability | — | 2002-09-17 |
| 6442098 | High performance multi-bank compact synchronous DRAM architecture | — | 2002-08-27 |
| 6434040 | Loadless NMOS four transistor SRAM cell | Tae H. Kim | 2002-08-13 |
| 6411538 | Compact load-less static ternary CAM | — | 2002-06-25 |
| 6343029 | Charge shared match line differential generation for CAM | Steve Lim | 2002-01-29 |
| 6331961 | DRAM based refresh-free ternary CAM | Hemraj K. Hingarh | 2001-12-18 |
| 6292416 | Apparatus and method of reducing the pre-charge time of bit lines in a random access memory | Chitranjan N. Reddy | 2001-09-18 |
| 6288922 | Structure and method of an encoded ternary content addressable memory (CAM) cell for low-power compare operation | Hing Wong | 2001-09-11 |
| 6259634 | Pseudo dual-port DRAM for simultaneous read/write access | Jawji Chen | 2001-07-10 |
| 6240008 | Read zero DRAM | Hemraj K. Hingarh | 2001-05-29 |
| 6141236 | Interleaved stitch using segmented word lines | — | 2000-10-31 |
| 6137746 | High performance random access memory with multiple local I/O lines | Chitranjan N. Reddy | 2000-10-24 |
| 6108250 | Fast redundancy scheme for high density, high speed memories | — | 2000-08-22 |
| 5872742 | Staggered pipeline access scheme for synchronous random access memory | Darryl G. Walker, Kenneth A. Poteet, Chitranjan N. Reddy | 1999-02-16 |
| 5831315 | Highly integrated low voltage SRAM array with low resistance Vss lines | Chitranjan N. Reddy | 1998-11-03 |
| 5808959 | Staggered pipeline access scheme for synchronous random access memory | Darryl G. Walker, Kenneth A. Poteet, Chitranjan N. Reddy | 1998-09-15 |
| 5717645 | Random access memory with fast, compact sensing and selection architecture | Chitranjan N. Reddy | 1998-02-10 |
| 5629646 | Apparatus and method for power reduction in dRAM units | Vinod Menezes, Raghava Madhu | 1997-05-13 |
| 5612635 | High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage | Raghava Madhu | 1997-03-18 |