Issued Patents All Time
Showing 76–100 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11171157 | Method for forming a MFMIS memory device | Chung-Te Lin | 2021-11-09 |
| 11094361 | Transistorless memory cell | Katherine H. Chiang, Chung-Te Lin, Min Cao, Yuh-Jier Mii | 2021-08-17 |
| 11081493 | Method for forming semiconductor memory device with sacrificial via | Chung-Te Lin | 2021-08-03 |
| 11037952 | Peripheral circuitry under array memory device and method of fabricating thereof | Chung-Te Lin | 2021-06-15 |
| 10991756 | Bipolar selector with independently tunable threshold voltages | Chung-Te Lin, Min Cao, Randy B. Osborne | 2021-04-27 |
| 10978473 | Flash memory structure and method of forming the same | Chung-Te Lin, Yung-Yu Chen | 2021-04-13 |
| 10971682 | Method for fabricating memory device | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2021-04-06 |
| 10879458 | Memory device | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2020-12-29 |
| 10644231 | Memory device and fabrication method thereof | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2020-05-05 |
| 9583350 | Memory device and method for fabricating the same | Wei-Chen Chen | 2017-02-28 |
| 9419010 | High aspect ratio etching method | Yen-Hao Shih, Chih-Ping Chen | 2016-08-16 |
| 9356040 | Junction formation for vertical gate 3D NAND memory | — | 2016-05-31 |
| 8987700 | Thermally confined electrode for programmable resistance memory | Hsiang-Lan Lung, Matthew J. Breitwisch | 2015-03-24 |
| 8975687 | Nonvolatile memory array with continuous charge storage dielectric stack | Hang-Ting Lue, Tzu-Hsuan Hsu | 2015-03-10 |
| 8946671 | Mask read only memory containing diodes and method of manufacturing the same | Hsiang-Lan Lung, Yi-Chou Chen | 2015-02-03 |
| 8378410 | Semiconductor device and method of manufacturing the same | Hang-Ting Lue | 2013-02-19 |
| 8343840 | Blocking dielectric engineered charge trapping memory cell with high speed erase | Hang-Ting Lue, Chien-Wei Liao | 2013-01-01 |
| 8330210 | High-κ capped blocking dielectric bandgap engineered SONOS and MONOS | Hang-Ting Lue, Chien-Wei Liao | 2012-12-11 |
| 8207571 | Non-volatile memory device with a threshold voltage change rate controlled by gate oxide phase | Hang-Ting Lue | 2012-06-26 |
| 8119481 | High-κ capped blocking dielectric bandgap engineered SONOS and MONOS | Hang-Ting Lue, Chien-Wei Liao | 2012-02-21 |
| 7910981 | Semiconductor device and method of manufacturing the same | Hang-Ting Lue | 2011-03-22 |
| 7880115 | Method for laser annealing to form an epitaxial growth layer | Ruichen Liu | 2011-02-01 |
| 7816727 | High-κ capped blocking dielectric bandgap engineered SONOS and MONOS | Hang-Ting Lue, Chien-Wei Liao | 2010-10-19 |
| 7737488 | Blocking dielectric engineered charge trapping memory cell with high speed erase | Hang-Ting Lue, Chien-Wei Liao | 2010-06-15 |
| 7247503 | Method of laser annealing to form an epitaxial growth layer | Ruichen Liu | 2007-07-24 |